Computer graphics processing and selective visual display system – Plural physical display element control system – Display elements arranged in matrix
Reexamination Certificate
2001-07-31
2004-08-17
Eisen, Alexander (Department: 2674)
Computer graphics processing and selective visual display system
Plural physical display element control system
Display elements arranged in matrix
C345S084000
Reexamination Certificate
active
06778155
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to spatial light modulator (SLM) projection displays and more specifically to an improved clocking method for improved display performance.
2. Description of the Related Art
To achieve a satisfactory degree of intensity resolution in a display system using pulse width modulation (PWM), some display time periods (bit times) can be shorter than the time required to reload the pixels of the SLM. For some SLMs, for example a digital micromirror device™ (DMD™), a technique for displaying such short bit times, called reset/release, causes the DMD mirrors to be released (to float in a flat state). Typically the DMD mirrors operate with dark field projection optics in a binary ON/OFF manner, for example mirrors tilted +10° (binary 1 memory state under the mirrors) are ON and reflect light into the aperture of a projection lens while mirrors tilted −10° (binary 0 memory state under the mirrors) reflect light into a ‘dark trap’ away from the projection lens. As a result, flat 0° mirrors are in an ambiguous state, which can allow stray light to enter the aperture, so as to degrade the contrast and exhibit undesirable memory effects. In addition, when used in a system incorporating the socalled block-reset technique, two additional artifacts can occur; i.e., (1) horizontal lines at the reset block boundaries, and (2) a “venetian blind” effect across the reset blocks.
FIG. 1
is a binary PWM sequence pattern for a SLM. The first diagram
10
shows one frame refresh period for a 5-bit binary system (5-bits are used for simplification, typical systems use 8-bits or more) with bits ranging from the least significant bit (LSB)
100
to the most significant bit (MSB)
104
. Bit
0
100
, the LSB, accounts for 1/(2
n
-1) of the refresh period, where n is the number of bits. Then each succeeding bit represents double the time of its preceding bit; e.g., bit
1
101
represents 2× LSB, bit
2
102
represents 4× LSB, bit
3
103
represents 8× LSB, bit
4
104
represents 16× LSB, of the total refresh time. In a DMD, the memory cell under the mirror is addressed in a binary fashion according to this PWM sequence. The mirrors tilt ±X degrees depending on the binary state of its memory cell; e.g.; a mirror might tilt +10° if its associated memory cell has a binary 1 state and −10° if its memory cell has a binary 0 state. The second diagram
11
is an example of a memory cell, whose PWM sequence is binary 01111. When bit
0
,
1
,
2
, or
3
is loaded, the memory cell is a binary state
1
and when reset to this state the mirror is ON and reflects light into the lens aperture. When bit
4
is loaded, the memory cell is a binary state
0
and when reset to this state the mirror is OFF and reflects light away from the lens aperture into a ‘dark trap’. In this case, the mirror reflects light for {fraction (15/31)} or 48% of the refresh period and is dark for {fraction (16/31)} or 52% of the refresh period, since the MSB is a binary 0.
The human visual system effectively integrates the pulsed light from the mirror to form the perception of a level of light intensity. The gray scale level is proportional to the percentage of time the mirror is ON during the refresh time. The 48% level of the above example represents a gray level near the middle of the scale from black to white intensity. Similarly, the third diagram
12
is an example of a memory cell, whose PWM sequence is binary 11010. When bit
1
,
3
or
4
is loaded, the memory cell is a binary state
1
and when reset to this state the mirror is ON and reflects light into the lens aperture. When bit
0
or
2
is loaded, the memory cell is a binary state
0
and when reset to this state the mirror is-OFF and reflects light away from the lens aperture into a ‘dark trap’. In this case, the mirror reflects light for {fraction (26/31)} or 84% of the refresh period and is dark for {fraction (5/31)} or 16% of the refresh period.
In a PWM SLM (example DMD), the device is loaded with the MSB and left for approximately ½ the refresh time, then loaded with the second MSB and left for ¼ the refresh time, then loaded with the third MSB and left for ⅛ the refresh time, and so on until the LSB is loaded and left for 1/(2
n
-1) of the refresh time. However, it is not necessary to load and reset a bit and leave it for the full duration of time. Instead, the longer MSB periods can be broken into smaller segment, which are distributed throughout the refresh time and the mirror is addressed multiple times so as to add up to the total bit period duration. This technique, called “bitsplitting,” is illustrated in FIG.
2
and can create a more pleasing image over that of leaving the mirror in one position for the whole bit period. The first diagram
20
shows the PWM-example of
FIG. 1
using “bit-splitting”. If the SLM is a DMD, the memory cells can be loaded without affecting the state of the mirrors since the mirror superstructure has an inherent mechanical latch that allows the mirrors, once reset, to remain in that state independent of the memory cell state until the mirrors are once again reset. As a result, the cells can be loaded without upsetting the previous mirror state. It is desirable to continuously load the memory and reset the mirrors after equal intervals of time. In the diagram
20
bit
1
is loaded once during the refresh period and left for a period of time. Bit
2
is loaded twice during the refresh period and left each time for the same time as bit
1
. Similarly, bits
3
and
4
are loaded
4
and eight times, respectively, during the refresh period and each time left for the same period of time as bit
1
. However, notice in the diagram that bit
0
is loaded and left in its state for a period of time equal to only ½ that of bit
1
. The reason for this is that bit
0
has only ½ the weight of bit
1
. In this example, there is not enough time to load the memory array during bit
0
. Herein lies the problem to be address by this invention. But first, the second diagram
21
shows the “bitsplitting” example for the 48% intensity level discussed in FIG.
1
. Here bit
1
is a binary 1 for one split-bit (sb) period, bit
2
is a binary 1 for two separate sb periods, bit
3
is a binary 1 for four separate sb periods, and bit
4
is a binary 0 for eight sb periods, but bit
0
is a binary 1 for only ½ split-bit period. Similarly, the third diagram
22
shows the “bit-splitting” example for the 84% intensity level discussed in FIG.
1
. Here bit
0
is a binary 0 for ½ a split-bit period, bit
1
is a binary 1 for one split-bit (sb) period, bit
2
is a binary 0 for two separate sb periods, bit
3
is a binary 1 for four separate sb periods, and bit
4
is a binary 1 for eight sb periods.
SLMS, and DMDs in particular, have typically been addressed globally; i.e., all cells are addressed and then reset simultaneously, as illustrated in FIG.
3
. While data is being loaded into the DMD, the mirrors remain in their previous state due to a bias voltage, which is applied to the mirror superstructure. That is, after the device is loaded with the new data bit plane, the bias voltage is reset, allowing the mirrors to assume their respective state corresponding to this new bit plane.
FIG. 3
shows the memory being loaded, the reset pulse, the corresponding multiple split-bits being displayed, and the PWM sequence for the bits. For example, in operation, while bit
3
is displayed
30
, bit
4
is being loaded into memory
31
. Once bit
4
is loaded, the reset pulse
32
is applied causing the mirrors to go to the new bit
4
state
33
. Then while bit
4
is displayed
33
, bit
2
is loaded into memory
34
and the reset pulse
35
is applied causing the mirrors to go to the next bit state
2
36
, and so on throughout the PWM sequence
37
.
As mentioned earlier, a fundamental limitation of this load-reset method occurs when a split-bit (bit
0
) requires a shorter display dur
Doherty Donald B.
Hewlett Gregory J.
Brady III Wade James
Brill Charles A.
Eisen Alexander
Telecky , Jr. Frederick J.
Texas Instruments Incorporated
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