Active solid-state devices (e.g. – transistors – solid-state diode – Gate arrays
Reexamination Certificate
2002-03-01
2004-12-28
Lee, Hsien Ming (Department: 2823)
Active solid-state devices (e.g., transistors, solid-state diode
Gate arrays
C257S211000, C257S311000, C257S316000, C438S229000, C438S299000, C438S303000, C438S586000, C438S587000
Reexamination Certificate
active
06835970
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly, to a semiconductor device having self-aligned contact pads (SACs) and a method for manufacturing the same.
2. Description of the Related Art
As the integration density of semiconductor devices increases, gaps between adjacent devices disposed within the semiconductor devices decrease, and an area occupied by each of the semiconductor devices decreases. Accordingly, the area of a contact region continues to decrease, and contact margins also become reduced. Thus, alignment margins required in a photolithographic process become reduced. Recently, a method for manufacturing self-aligned contact pads in a highly integrated semiconductor device, which is capable of increasing alignment margins, has been suggested.
A conventional semiconductor device having self-aligned contact pads (SACs) and a method for manufacturing the same will be described with reference to
FIGS. 1
,
2
,
3
A,
3
B,
4
A, and
4
B.
FIGS. 1 and 2
are plan views illustrating a portion of a semiconductor device having SACS, where the semiconductor device is made using a conventional manufacturing method.
FIGS. 3A and 3B
are views illustrating a cross section of a semiconductor substrate taken along lines a-a′ and b-b′, respectively, of FIG.
1
.
FIGS. 4A
and
4
B are views illustrating a cross section of a semiconductor substrate taken along lines a-a′ and b-b′, respectively, of FIG.
2
.
Referring to
FIGS. 1
,
3
A, and
3
B, an isolation layer
20
is formed to define active regions
15
on a semiconductor substrate
10
. The active regions
15
each have a major axis and a minor axis. A plurality of gates
35
are formed on the semiconductor substrate
10
to cross the active regions
15
and extend in the direction of the minor axis of each of the active regions
15
. Each of the gates
35
includes a stacked structure comprised of a gate insulating layer
22
, a gate electrode
25
, and a capping layer
27
, and spacers
30
formed to surround the sidewalls of each of the stacked structures. Two gates
35
are disposed on each of the active regions
15
. Here, the capping layer
27
and the spacers
30
are formed of a nitride layer which has a different etching selectivity from that of an interlayer insulating layer to be formed in a subsequent process.
Next, impurities are implanted into the active regions
15
at either side of each of the gates
35
, thereby forming a first source/drain region
40
a
and a second source/drain region
40
b.
An interlayer insulating layer
45
is formed to completely fill a gap between adjacent gates
35
, and then the top surface of the interlayer insulating layer
45
is planarized.
Next, photoresist patterns
50
used to form SACs are formed into an island shape on the interlayer insulating layer
45
. The photoresist patterns
50
are formed to have the same size as the active regions
15
at rows where the active regions
15
are not formed.
Referring to
FIGS. 2
,
4
A, and
4
B, the interlayer insulating layer
45
is etched using the photoresist patterns
50
as etching masks so that first and second contact holes H
11
and H
12
are formed to expose the top surfaces of the first and second source/drain regions
40
a
and
40
b,
respectively. The photoresist patterns
50
are removed, and then a doped polysilicon layer is formed to completely fill the first and second contact holes H
11
and H
12
. The top surfaces of the doped polysilicon layer and the interlayer insulating layer
45
are planarized to expose the top surface of the capping layer
27
. Thus, first and second SACs
55
a
and
55
b
are formed to directly contact the top surfaces of the first and second source/drain regions
40
a
and
40
b,
respectively.
During the etching process for forming the first and second contact holes H
11
and H
12
, an etching gas, such as C
4
F
8
or C
5
F
8
, is used in order to make the interlayer insulating layer
45
have a high etching selectivity with respect to a nitride layer. However, during the etching process using such an etching gas, a considerable amount of polymer may be generated. If the aspect ratio of a contact hole is high, polymer generated during etching cannot be removed from the contact hole, and thus the etching process may be easily stopped. Accordingly, in order to prevent such a phenomenon, the interlayer insulating layer
45
is over-etched by increasing the etching time.
If the area occupied by the photoresist patterns
50
is small, the uppermost portion of the photoresist patterns
50
may be deformed during over-etching of the interlayer insulating layer
45
. In addition, the photoresist patterns
50
may collapse because the photoresist patterns
50
formed into an island shape are weak. In particular, since the edge of each of the photoresist patterns
50
is thinly formed, adjacent first SACs
55
a
are not completely isolated from each other, and a bridge is generated between the adjacent first SACs
55
a.
The amount of etching gas required in etching is proportional to the area of material to be etched, and thus the etch rate of a contact hole having a large width is lower than the etch rate of a contact hole having a small width. If the photoresist patterns
50
are formed in an island shape, the first contact hole H
11
, in which the first SAC
55
a
will be formed, has a width smaller than the second contact hole H
12
, in which the second SAC
55
b
will be formed. Thus, the etching rate of the first contact hole H
11
is different from the etching rate of the second contact hole H
12
. Accordingly, if the amount of etching gas is determined in consideration of the size of only one of the first and second contact holes H
11
and H
12
, it is difficult to form the other contact hole in a desired shape.
SUMMARY OF THE INVENTION
To solve the above and other related problems of the prior art, there is provided a semiconductor device in which adjacent self-aligned contact pads (SACs) are completely isolated from one another. Moreover, there is provided a method for manufacturing a semiconductor device having SACs, that overcomes the prior art problem of irregular etching of the contact holes in which the SACs are formed due to different contact hole widths.
According to an aspect of the present invention, there is provided a semiconductor device that comprises a semiconductor substrate. An isolation layer is formed on the semiconductor substrate for defining a plurality of active regions. Each of the plurality of active regions has a major axis and a minor axis. A plurality of gates are formed to cross the plurality of active regions and extend in a direction of the minor axis of each of the plurality of active regions. Each of the plurality of gates has a first side and a second side that are opposing and that run along the direction of the minor axis. A plurality of first and second source/drain regions are formed in the plurality of active regions at either of the first side or the second side of each of the plurality of gates. Each of the plurality of first and second source/drain regions has a top surface. A plurality of first self-aligned contact pads (SACs) and a plurality of second SACs are formed to contact the top surface of each of the plurality of first and second source/drain regions, respectively.
According to another aspect of the present invention, each of the plurality of second SACs have sidewalls and a top surface. The isolation layer has a top surface. An arrangement of the plurality of second SACs forms a plurality of columns. An arrangement of the plurality of first SACs forms a plurality of first rows having a plurality of second rows disposed in an alternating arrangement there between. The semiconductor device further comprises a plurality of contact plugs and a plurality of bit lines. Each of the plurality of contact plugs has a top surface. Each of the plurality of contact plugs is formed to contact
Chae Yun-sook
Kim Ji-soo
Nam Dong-seok
F. Chau & Associates LLC
Lee Hsien Ming
LandOfFree
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