Multiplex communications – Pathfinding or routing – Switching a message which includes an address header
Reexamination Certificate
1999-06-25
2004-08-24
Chin, Wellington (Department: 2664)
Multiplex communications
Pathfinding or routing
Switching a message which includes an address header
C370S422000
Reexamination Certificate
active
06781986
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to a method, apparatus and system for a scalable high capacity switch architecture and more particularly to one which employs distributed control.
2. Description of Related Art
A switch is a basic component of most telecommunications networks. Switches permit a large number of source devices to communicate with each of a large number of destination devices over a relatively smaller number of communications trunks. Information is sent over the communications trunks as discrete packets or cells of digital information, representing either data or voice transmissions, for example. Packet or cell transmission from a source device to a destination device must be maintained within narrow time parameters if an acceptable quality of service is to be maintained.
There are many different switch architectures. One architecture has a “shared memory” in which packets, each having a unique destination address corresponding to an output port, arrive from a plurality of input ports and are stored in a shared buffer located in a shared memory. A plurality of output ports has access to the shared memory and each output port is enabled to read packets addressed to it. A centralized controller controls read/write access to the memory to prevent contention between accessing devices. However, the scalability of the device is limited by the capacity of the centralized controller and the switching speed is limited by the memory access speed. Furthermore, the switch suffers from resiliency problems, as a failure of the centralized controller will disable the switch as a whole.
A similar architecture replaces the shared memory in the switch described above, with a space switch which establishes connections between individual input ports and output ports to permit transmission of a burst of packets, after which the connections are broken. Arbitration logic is provided to deal with contention that is, two or more input ports attempting to establish links with a single output port at the same time. The arbitration logic is linked to a centralized controller which controls the space switch and thereby controls access to the output ports. Like the shared memory architecture, this device suffers from resiliency and scalability problems due to the centralized nature of the controller. Furthermore, the control regime must be optimized to compromise between switching overhead and quality of service. If the burst length is too long, quality of service may be compromised as contending input ports are left unserved for unacceptably long time periods. If the burst length is too short, switching overhead increases to unacceptable levels.
With the increasing volume of packet traffic, it is desirable to increase the speed and capacity of switches to the range of terabits of information per second and beyond. In order to do this cost effectively, it is desirable to use a plurality of input devices in parallel, each having a capacity of 10 gigabits per second, for example. However, if a centralized controller is necessary to arbitrate contention between the plurality of input devices, the upper limit of the capacity of the switch is set by the centralized controller, and the scalability is limited. Instead, it would be desirable to distribute the control function among a plurality of switching controllers, each with its own bank of input ports, to facilitate scalability of input ports and switching capacity to increase switch throughput.
SUMMARY OF THE INVENTION
To address the above shortcomings, there is provided a scalable high capacity switch architecture which employs a distributed control regime to permit efficient use of bandwidth while preventing contention. A switch having this architecture has a plurality of input switching controllers, a plurality of output switching modules, and a cross bar switch located therebetween. Each switching controller determines whether any other switching controller in the switch intends to transmit to a particular destination at a particular time and if no other switching controller intends to transmit to such destination, the switching controller transmits to that destination. In this manner, bandwidth unused by other switching controllers can be used by one or more switching controller to transmit packets when they would not normally transmit such packets. Knowledge of intention to transmit is passed among the switching controllers to allow each switching controller to consider the intentions of the others to determine whether or not to transmit when others are not transmitting. Thus, it may be said that the system distributes control of when to transmit among all of the switching controllers.
In accordance with one aspect of the invention there is provided a method of operating a switching controller in a system comprised of a plurality of switching controllers. The method involves receiving a data packet at the switching controller and determining a destination of the data packet. The switching controller then determines whether any other switching controller in the system intends to transmit to the determined destination of the packet and transmits the received data packet to the determined destination at a time interval when no other switching controller intends to transmit to the determined destination.
In one embodiment, the switching controller receives an input schedule from another switching controller in the system specifying when other switching controllers in the system will not be transmitting to respective destinations.
In accordance with another aspect of the invention, there is provided a switching controller apparatus for use in a system comprised of a plurality of switching controllers. The apparatus includes a data packet receiver for receiving a data packet and a processor for determining the destination of the data packet. The processor also determines whether any other switch controller intends to transmit to the determined destination of the packet at a given time. The apparatus further includes a transmitter for transmitting the received data packet to the determined destination when no other switch controller intends to transmit to the determined destination.
In accordance with another aspect of the invention, there is provided a switching system including a plurality of switching modules, a crossbar switch in communication with the switching modules and a plurality of switching controllers in communication with the switching modules through the crossbar switch. The switching controllers are configured to communicate with each other to permit a data packet to be transmitted to its destination from a switching controller, at a time when the switching controller is not scheduled to transmit to the destination.
In accordance with another aspect of the invention there is provided a method of operating a plurality of switching controllers, the method comprising receiving data packets at respective switching controllers and transmitting the data packets from the switching controllers to their destinations according to a predefined schedule. The method also includes communicating among the switching controllers to permit a data packet to be transmitted from at least one switching controller to its destination at a time when that switching controller is not scheduled to transmit to that destination.
In accordance with another aspect of the invention, there is provided a switching controller apparatus for use in a system comprised of a plurality of switching controllers. The switching controller apparatus includes a unit for receiving a data packet, a unit for determining a destination of the data packet, a unit for determining whether any other switching controller in the system intends to transmit to the determined destination of the data packet and a unit for transmitting the received data packet to the determined destination when no other switching controllers intend to transmit to the determined destination.
Other aspects and features of the present invention will become apparent to
El-Etr Ibrahim
Sabaa Amr G.
Chin Wellington
Jain Raj
Nortel Networks Limited
LandOfFree
Scalable high capacity switch architecture method, apparatus... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Scalable high capacity switch architecture method, apparatus..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Scalable high capacity switch architecture method, apparatus... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3323292