Boots – shoes – and leggings
Patent
1994-12-14
1996-04-16
Treat, William M.
Boots, shoes, and leggings
395800, 364DIG1, G06F 938
Patent
active
055091300
ABSTRACT:
In a pipelined processor, an instruction queue and an instruction control unit is provided to group and issue m instructions simultaneously per clock cycle for execution. An integer and a floating point function unit capable of generating n.sub.1 and n.sub.2 integer and floating point results per clock cycle respectively, where n.sub.1 and n.sub.2 are sufficiently large to support m instructions being issued per clock cycle, is also provided to complement the instruction queue and instruction control unit. The pipeline stages are divided into integer and floating point pipeline stages where the early floating point stages overlap with the later integer pipeline stages. The instruction queue stores sequential instructions of a program and target instructions of a branch instruction of the program, fetched from the instruction cache. The instruction control unit decodes the instructions, detects operands cascading from instruction to instruction, group instructions into instruction groups of at most m instructions applying a number of exclusion rules, and issuing the grouped instructions simultaneously to the integer and/or floating point unit for execution. The exclusion rules reflect the resource characteristics and the particular implementation of the pipelined processor. The instruction control unit also tracks the history of the instruction groups and uses the history in conjunction with the exclusion rules in forming the instruction groups.
REFERENCES:
patent: 5129067 (1992-07-01), Johnson
patent: 5136697 (1992-08-01), Johnson
patent: 5226126 (1993-07-01), McFarland et al.
patent: 5226130 (1993-07-01), Favor et al.
patent: 5230068 (1993-07-01), Van Dyke et al.
Machine organization of the IBM RISC System/6000 processor, Author: G. F. Grohoski; Publication: IBM Journal of Research & Development, vol. 34 No. 1, Jan. 1990.
A High Speed Superscalar PA-RISC 7100 Processor, Authors: Eric DeLano, Will Walker, Jeff Yetter, Mark Forsyth; Publication: Digest of Papers Compcon, Spring 1992.
The Motorola 88110 Superscalar RISC Microprocessor, Authors: Keith Diefendorff & Michael Allen; Publication: Digest of Papers Compcon, Spring 1992.
Abu-Nofal et al., "A Three-Million-Transistor Microprocessor," 1992 IEEE Solid-State Circuits Conference. Digest of Technical Papers, Feb. 19-21, 1992, pp. 108-109.
Kohn et al., "Introducing the Intel i860 64-Bit Microprocessor," IEEE Micro, Aug. 1989, pp. 15-30.
Lightner et al., "The Metaflow Lightning Chipset," Compcon Spring '91, IEEE, Conference Paper, Feb. 25-Mar. 1, 1991, pp. 13-18.
Popescu et al., "the Metaflow Architecture," IEEE Micro, Jun. 1991, pp. 10-13 and 63-73.
David J. Lilja, "Reducing the Branch Penalty in Piplined Processors," Computer, IEEE, Jul. 1988, pp. 47-55.
Smith et al., "Implementing Precise Interrups in Piplined Processors," IEEE Transactions on Computers, vol. 37, No. 5, May 1988, pp. 562-573.
Nanda Sunil
Trauben Richard D.
Sun Microsystems Inc.
Treat William M.
LandOfFree
Method and apparatus for grouping multiple instructions, issuing does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method and apparatus for grouping multiple instructions, issuing, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method and apparatus for grouping multiple instructions, issuing will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-332239