Method of fabricating a stringerless flash memory

Details Method of fabricating a stringerless flash memory Method of fabricating a stringerless flash memory

2002-03-25

2004-10-12

Goudreau, George A. (Department: 1763)

Cleaning and liquid contact with solids

Processes

Including application of electrical radiant or wave energy...

C134S001300, C438S714000, C438S725000, C438S734000, C438S750000, C438S696000

Reexamination Certificate

active

06802322

ABSTRACT:

BACKGROUND OF INVENTION
1. Field of the Invention
The present invention relates to a method of fabricating a flash memory, and more particularly, to a method of fabricating a stringerless flash memory to prevent stringer leakage and improve data retention ability.
2. Description of the Prior Art
EEPROM (electrically erasable programmable read only memory) is a very popular memory device used in the electronics industry due to its ability to store data in a non-volatile manner for more than 10 years, and with the capability of being reprogrammed or erased many times. However, one disadvantage of EEPROM devices is their slow memory access time compared to other memory devices. In order to solve this problem, a flash EEPROM device was developed by Intel. In contrast to the traditional EEPROM, the flash EEPROM can erase recorded data a block at a time instead of a byte at a time, to dramatically increase the memory access speed.
Please refer to FIG.
1
.
FIG. 1
is a cross-sectional diagram of a prior flash memory cell
30
. As shown in
FIG. 1
, the flash memory cell
30
comprises a substrate
10
, a floating gate
17
, an ONO dielectric layer
18
and a polysilicon word line
20
. The floating gate
17
, comprising a first polysilicon layer
14
and a second polysilicon layer
16
, is positioned between an insulating layer
12
a
and
12
b
. Doped regions
11
a
and
11
b
, function as a bit line of the flash memory cell
30
, are formed beneath the insulating layer
12
a
and
12
b
, respectively. The doped regions
11
a
and
11
b
may also function as a buried drain. In addition, an oxide layer
13
is positioned between the floating gate
17
and the substrate
10
. Hot electrons tunnel through the oxide layer
13
to get in or get out of the floating gate
17
, thus achieving data accessing.
However during the fabrication process of the flash memory cell
30
, a polysilicon residue
22
occurs to induce current leakage problems, so the data retention ability of the memory cell is thus reduced. Please refer to
FIG. 1
, while the insulating layer
12
a
and
12
b
intersect the substrate
10
at an angle &thgr; greater than 90 degrees, the polysilicon residue
22
will remain on the side wall of the insulating layer
12
a
and
12
b
as a result of an etching process to define patterns of the word line
20
, the first polysilicon layer
14
and the second polysilicon layer
16
. The polysilicon residue
22
may also be called a stringer.
SUMMARY OF INVENTION
It is therefore a primary objective of the present invention to provide a method of fabricating a flash memory to solve the above-mentioned problems.
It is another objective of the present invention to provide a method of fabricating a stringerless flash memory to achieve better reliability for the flash memory.
It is another objective of the present invention to provide a method of fabricating a stringerless flash memory to increase the process window.
According to the claimed invention, a semiconductor substrate is first provided. A silicon oxide layer is formed on the semiconductor substrate. After that, a plurality of rows of layer stacks is formed on the silicon oxide layer, a shallow trench being formed between two adjacent layer stacks. Each layer stack comprises a first polysilicon layer and a sacrificial layer, and has two side walls. Wherein, each side wall of the layer stack intersects the bottom of the shallow trench at an angle greater than 90 degrees. Then, a spacer is formed on each side wall of the layer stacks followed by the deposition of a high density plasma (HDP) silicon oxide layer to cover the layer stacks and the shallow trenches. The HDP silicon oxide layer is planarized to expose the sacrificial layer. The sacrificial layer and a portion of the spacer are removed, such that a remainder of the spacer forms a stringer block. Thereafter, a second polysilicon layer is formed on the first polysilicon layer, the first polysilicon layer combining with the second polysilicon layer to form a floating gate layer. An insulating layer and a controlling gate layer are formed on the floating gate layer, then an anisotropic dry etching process is performed to remove portions of the controlling gate layer, the insulating layer and the floating gate layer. Following the etching process of the floating gate layer, a bottom corner stringer is formed beside the stringer block during. Finally, the stringer block is removed to expose the bottom corner stringer followed by removal of the bottom corner stringer.
It is an advantage of the present invention that the stringer block is formed on the interface between the HDP silicon oxide layer and the silicon substrate. Thus, the bottom corner stringer can be exposed following the removal of the stringer block and removed by a dry etching process. As a result, a stringerless flash memory cell is formed to prevent leakage currents resulting from the bottom corner stringers according to the present invention. In addition, both the reliability and data retention ability of the flash memory cell are effectively improved.
These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment, that is illustrated in the various figures and drawings.


REFERENCES:
patent: 6004878 (1999-12-01), Thomas et al.
patent: 6191444 (2001-02-01), Clampitt et al.
patent: 6699753 (2004-03-01), Ma et al.

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