MOS integrated circuit with vertical shield

Details MOS integrated circuit with vertical shield MOS integrated circuit with vertical shield

1988-12-19

1990-09-25

Carroll, J.

357 2313, 357 40, 357 45, 357 71, H01L 2906, H01L 2702, H01L 2710, H01L 2348

Patent

active

049597086

ABSTRACT:
A MOS integrated circuit in which a plurality of MOS devices on a substrate are interconnected with each other and with signal, power and ground pads in first and second electrical circuits adapted to process separate electrical signals. The pads are formed of first metal members below a passivation layer and second metal members in a second metallization layer projecting through openings in the passivation layer to contact the first metal members. A pair of adjacent signal carrying elements in the first and second electrical circuits subject to crosstalk through a horizontal parasitic capacitance of the passivation layer are shielded by a first metal member of the first metallization layer and a second metal member of the second metallization layer connected to the first metal member and extending through and above the passivation layer to block the capacitive coupling therethrough, the first and second metal members being grounded to the ground pad through the first metallization layer below the passivation layer or through the second metallization layer above the passivation layer.

REFERENCES:
patent: 4378628 (1983-04-01), Levinstein et al.
patent: 4509067 (1985-04-01), Minami et al.
patent: 4628343 (1986-12-01), Komatsu
patent: 4724471 (1988-02-01), Leuschner
patent: 4780846 (1988-10-01), Tanabe et al.
patent: 4825280 (1989-04-01), Chen et al.

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