Semiconductor integrated circuit with sleep memory

Details Semiconductor integrated circuit with sleep memory Semiconductor integrated circuit with sleep memory

2003-08-12

2004-12-28

Zweizig, Jeffrey (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Specific identifiable device, circuit, or system

With specific source of supply or bias voltage

Reexamination Certificate

active

06836175

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor integrated circuit, more particularly to a semiconductor integrated circuit that operates at high speed on a low power supply voltage in an active state, but consumes little power in a sleep state.
2. Description of the Related Art
The increasing levels of integration and performance attained by semiconductor integrated circuits have widened their range of application into areas in which low power consumption is an important consideration. The power consumption of a complementary metal-oxide-semiconductor (CMOS) integrated circuit varies in proportion to the square of its power supply voltage, so the most effective way to reduce power consumption is to lower that voltage. Lowering the power supply voltage, however, reduces the operating speed of metal-oxide-semiconductor (MOS) transistors, unless the transistor threshold voltage is also lowered, and if the transistor threshold voltage is lowered, subthreshold current leakage rises. This leakage greatly increases power consumption in the standby state or sleep state, in which the integrated circuit is powered but is not active.
A solution to this problem is to provide a CMOS integrated circuit with low-threshold transistors for use in the active state, and higher-threshold transistors for preserving necessary data in the sleep state. A multi-threshold CMOS (MTCMOS) circuit of this type is described by S. Shigematsu et al. in “A 1-V High-Speed Circuit Scheme for Power-Down Application Circuits”, IEEE J. Solid State Circuits, Vol. 32, No. 6 pp. 861-869 (June 1997), and will be described briefly below.
Referring to
FIG. 1
, a power-supply circuit (not shown) connected to a power line
1
and a ground line
2
supplies power at a voltage VDD in relation to a ground potential or voltage (GND). A virtual power line
3
and a virtual ground line
4
are also provided. The virtual power line
3
is coupled to the power line
1
through a p-channel MOS (PMOS) transistor
5
; the virtual ground line
4
is coupled to the ground line
2
through an n-channel MOS (NMOS) transistor
6
. A sleep control signal SL is supplied to the gate of NMOS transistor
6
, and through an inverter
7
to the gate of PMOS transistor
5
. In the active state, the sleep control signal SL is high, transistors
5
and
6
are switched on, and a virtual power-supply voltage VVDD and virtual ground VGND appear on the virtual power line
3
and virtual ground line
4
. Logic circuitry comprising transistors having a low threshold voltage is connected to the virtual power line
3
and virtual ground line
4
, and operates at high speed. In the sleep state, the sleep control signal SL is low, transistors
5
and
6
are switched off, and the supply of power to the logic circuitry is halted, thereby also halting current leakage.
If the logic circuitry includes circuits for storing data, the stored data will be lost when the virtual power supply is cut off. If the data must be retained during the sleep state, a separate sleep memory circuit is needed. For data stored in a clocked data storage circuit, it may also be necessary to store the state of the clock signal.
FIG. 2
illustrates a logic circuit for generating a pair of complementary clock signals from a clock input signal, and a first sleep memory circuit for storing the state of the clock input signal.
The logic circuit includes a transmission gate
11
through which the clock input signal CKI is supplied to a node N
11
. From node N
11
, the clock signal is output through a cascaded pair of inverters
12
,
13
. The outputs of the inverters
12
and
13
are denoted /CK and CK, respectively, the slash (/) indicating an inverted signal.
Node N
11
is also coupled through a transmission gate
14
to a node N
12
in a type of flip-flop
10
comprising inverters
15
,
16
and a transmission gate
17
, which are interconnected to form a loop. Flip-flop
10
and transmission gate
14
constitute a first sleep memory circuit.
Inverters
12
and
13
comprise low-threshold transistors (not shown) coupled to the virtual power line
3
and virtual ground line
4
, whereas inverters
15
and
16
comprise high-threshold transistors coupled to the power line
1
and ground line
2
. Transmission gate
14
comprises high-threshold transistors controlled by memory control signals B
1
and /B
1
, whereas the other two transmission gates
11
,
17
comprise low-threshold transistors controlled by memory control signals B
2
and /B
2
. The presence of low-threshold transistors in inverters and transmission gates is indicated in the drawings by thick lines on the input side of the circuit symbol.
FIG. 3
illustrates a clocked data storage circuit and a second sleep memory circuit for storing the internal state of the clocked data storage circuit. The clocked data storage circuit is controlled by the clock signals CK, /CK output from inverters
12
,
13
in FIG.
2
.
The clocked data storage circuit includes a transmission gate
21
that passes input data (IN) to a node N
21
connected to the input side of an inverter
22
. Inverter
22
is connected in a loop with another inverter
23
and a pair of transmission gates
24
,
25
to form a master flip-flop circuit. The output terminal of inverter
22
is connected to a node N
22
, which is coupled through a transmission gate
26
to a node N
23
. Node N
23
is connected to the input side of an inverter
27
, which is connected with an inverter
28
and a pair of transmission gates
29
,
30
in another loop, forming a slave flip-flop circuit. A data output signal (OUT) is obtained from the output terminal of inverter
27
.
Node N
21
is coupled to a node N
24
through a series of two transmission gates
31
,
32
. Node N
23
is coupled to node N
24
through another series of two transmission gates
33
,
34
. Node N
24
is connected to a flip-flop
20
comprising inverters
35
,
36
and a transmission gate
37
interconnected in a loop. Transmission gates
31
,
32
,
33
,
34
, and flip-flop
20
constitute a second sleep memory circuit.
Inverters
22
,
23
,
27
,
28
comprise low-threshold transistors coupled to the virtual power line
3
and virtual ground line
4
, whereas inverters
35
and
36
comprise high-threshold transistors coupled to the power line
1
and ground line
2
. Transmission gates
21
,
24
,
25
,
26
,
29
,
30
,
37
comprise low-threshold transistors, whereas transmission gates
31
to
34
comprise high-threshold transistors. Transmission gates
21
,
25
,
26
,
30
,
32
,
34
are controlled by clock signals CK, /CK; transmission gates
24
,
29
,
37
by memory control signals B
2
, /B
2
; and transmission gates
31
,
33
by memory control signals B
1
, /B
1
.
The operation of these prior-art circuits will be described with reference to FIG.
4
.
In the active state, the sleep control signal SL is driven high (H) and the memory control signals B
1
, B
2
are driven low (L). Since the sleep control signal SL is high, transistors
5
,
6
are switched on, the virtual power-supply voltage VVDD and virtual ground VGND are supplied to the virtual power line
3
and virtual ground line
4
, respectively, and logic circuitry such as inverters
12
,
13
,
22
,
23
,
27
,
28
becomes operational. Since memory control signals B
1
, B
2
are low, transmission gates
14
,
17
,
31
,
33
,
37
are switched off, and transmission gates
24
,
29
are switched on. Flip-flop
10
is electrically disconnected from node N
11
and disabled, flip-flop
20
is electrically disconnected from nodes N
21
, N
23
and disabled, and the flip-flops including inverters
22
,
23
,
27
,
28
are enabled. These flip-flops and other logic circuitry comprising low-threshold transistors operate at high speed, with low power consumption.
In the sleep-in state occurring at a transition from the active state to the sleep state, memory control signal Bi is driven high, switching on transmission gates
14
,
31
, and
33
. The signal at node N
11
is transferred to inver

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