Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Of specified configuration
Reexamination Certificate
2001-08-28
2004-11-02
Eckert, George (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Of specified configuration
C257S775000, C257S776000, C257S777000, C257S784000, C438S617000, C438S782000
Reexamination Certificate
active
06812575
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device, more specifically, it relates to a semiconductor device with a plurality of semiconductor chips stacked.
2. Detailed Description of the Related Art
FIG. 7
shows a conventional semiconductor device with a plurality of semiconductor chips
2
,
3
stacked on a substrate
1
. As a high density mounting technique, a technique of laminating and mounting a plurality of semiconductor chips on a substrate, called stack mounting is used.
In the stack mounting, in general, the substrate and the stacked semiconductor chips are connected by wire bonding. Therefore, the semiconductor chips are stacked from one with a larger chip size so as to prevent interference of a semiconductor chip stacked above with a bonding pad of a semiconductor chip disposed below.
Since the bonding pad on the substrate is provided around the semiconductor chip in the lowermost layer, the upper layer semiconductor chip with a smaller chip size has a longer distance with respect to the bonding pad on the substrate. Therefore, with a larger chip size difference in the upper layer and the lower layer, the distance between the bonding pad of the upper layer semiconductor chip and the bonding pad on the substrate becomes longer. In particular, the wire connecting the substrate to the chip becomes longer. Accordingly, the wire strength is lowered so that sagging of the wire by its own weight occurs. Tilting of the wire at the time of sealing, or the like is generated so as to deteriorate the yield, which is problematic.
FIG. 8
is a cross-sectional view of a semiconductor device disclosed in the unexamined Japanese Utility Model Publication (KOKAI) No. 2-146436.
The semiconductor device shown in
FIG. 8
is a hybrid IC with IC chips stacked in two stages with the IC chips butted with each other and connected by a solder bump, wherein only the lower chip
20
is wire bonded, because the lower IC chip
20
is formed larger than the upper IC chip
30
. However, according to the semiconductor device shown in
FIG. 8
, a problem is involved in that the lower semiconductor chip
20
should be provided with a pad matching with the upper semiconductor chip
30
, and further, the lower semiconductor chip
20
should be a dedicated semiconductor chip to serve as a pair with the upper semiconductor chip
30
.
SUMMARY OF THE INVENTION
Accordingly, an object of the present invention is to provide a novel semiconductor device with an improved yield by solving the problems in the above-mentioned conventional technology, in particular, by shortening the wire length per one loop so as to eliminate the problems of wire sagging by its own weight, tilting of the wire at the time of sealing, or the like.
In order to achieve the above-mentioned object, the present invention basically adopts the technological configurations described below.
That is, a first aspect of the present invention is a semiconductor device with a plurality of semiconductor chips stacked on a substrate, wherein the semiconductor device comprising; a wiring layer disposed so as to be sandwiched between the semiconductor chips, and a plurality of bonding pads, for connecting a bonding wire, provided on the wiring layer, thereto.
In the second aspect of the present invention, a connection wiring for connecting the bonding pads is provided in the wiring layer.
In the third aspect of the present invention, a plurality of bonding pads are disposed so as to surround a semiconductor chip stacked on an upper surface of the wiring layer.
In the fourth aspect of the present invention, a via hole is provided in the wiring layer, this via hole is connected to a bonding pad of a semiconductor chip disposed below the wiring layer.
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Eckert George
NEC Corporation
Ortiz Edgardo
Young & Thompson
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