Methods for manufacturing semiconductor devices and...

Details Methods for manufacturing semiconductor devices and... Methods for manufacturing semiconductor devices and...

2001-09-26

2004-08-31

Pham, Long (Department: 2814)

Semiconductor device manufacturing: process

Formation of electrically isolated lateral semiconductive...

Grooved and refilled with deposited dielectric material

C438S436000, C438S438000, C438S440000

Reexamination Certificate

active

06784078

ABSTRACT:

TECHNICAL FIELD
The present invention relates to semiconductor devices having a field effect transistor and methods for manufacturing the same, and more particularly, to semiconductor devices having a gate electrode that is formed from two or more layers and methods for manufacturing the same.
RELATED ART
Currently, there is a technique in which a gate electrode
230
of a MOS transistor
300
shown in FIG.
11
(
b
) is formed by a so-called damascene method. One example of a method for manufacturing a MOS transistor
300
using a technique in which its gate electrode
230
is formed by a damascene method is described below.
As shown in FIG.
10
(
a
), a gate dielectric layer
220
(also sometimes referred to as a gate insulation layer) and a dummy electrode
232
are formed on a silicon substrate
210
. Next, the dummy electrode
232
is patterned. Then, a low concentration impurity diffusion layer
242
is formed in the silicon substrate
210
on the sides of the dummy electrode
232
. Next, an insulation layer is formed over the entire surface, and the insulation layer and the gate dielectric layer
220
are etched by RIE to form sidewall spacers
250
on the side walls of the dummy electrode
232
. Then, a high concentration impurity diffusion layer
244
is formed in the silicon substrate
210
on the sides of the sidewall spacers
250
.
Next, as shown in FIG.
10
(
b
), an insulation layer
260
is formed on the silicon substrate
210
, and the insulation layer
260
is then planarized to expose the dummy electrode
232
.
Next, as shown in FIG.
11
(
a
), the entire dummy electrode
232
is removed to form a through hole
270
.
Next, as shown in FIG.
11
(
b
), a metal layer is formed in a manner to fill the through hole
270
, and the metal layer is then etched-back to form a gate electrode
230
.
Techniques to form gate electrodes by a damascene method are described in references such as U.S. Pat. Nos. 5,960,270, 5,391,510, 5,434,093.
SUMMARY
Embodiments include a method for manufacturing a semiconductor device, the method including forming a gate dielectric layer and forming a first conduction layer on the gate dielectric layer. The method also includes forming a first upper layer comprising a material different from the first conduction layer on the first conduction layer, and forming a second upper layer comprising a material different from the first upper layer on the first upper layer. Sidewall spacers are formed on side walls of the first conduction layer, the first upper layer and the second upper layer. The method also includes forming an insulation layer that covers the second upper layer and the sidewall spacers, and planarizing the insulation layer until an upper surface of the second upper layer is exposed. The method also includes removing the second upper layer, and removing the first upper layer to form a recessed section between the sidewall spacers. A second conduction layer is formed in the recessed section to form a gate electrode that includes at least the first conduction layer and the second conduction layer.
Embodiments also include a method for manufacturing a semiconductor device, the method including forming a gate dielectric layer and forming a first conduction layer on the gate dielectric layer. The method also includes forming an upper layer on the first conduction layer. At least a lower portion of the upper layer comprises a material different from at least an upper portion of the first conduction layer. Sidewall spacers are formed on side walls of the first conduction layer and the upper layer. An insulation layer is formed that covers the upper layer and the sidewall spacers. The insulation layer is planarized until an upper surface of the upper layer is exposed. The upper layer is removed to form a recessed section between the sidewall spacers on an upper portion of the first conduction layer. A second conduction layer is formed in the recessed section to form a gate electrode that includes at least the first conduction layer and the second conduction layer.
Embodiments also include a method for manufacturing a semiconductor device, the method including forming a gate dielectric layer and forming a first conduction layer on the gate dielectric layer. An upper layer is formed on the first conduction layer, the upper layer comprising a material different from that of the first conduction layer. Sidewall spacers are formed on side walls of the first conduction layer and the upper layer. The upper layer is removed to form a recessed section between the sidewall spacers and above at least part of the first conduction layer. A second conduction layer is formed in the recessed section to form a gate electrode comprising the at least part of the first conduction layer and the second conduction layer.
Other embodiments include a semiconductor device including a field effect transistor, the field effect transistor including a gate dielectric layer, a gate electrode, sidewall spacer regions, a source region, and a drain region. The gate electrode includes a first conduction layer and a second conduction layer. The first conduction layer is formed on the gate dielectric layer. The second conduction layer is formed above the first conduction layer. The sidewall spacer regions are formed on side walls of the gate electrode. An insulation layer is provided adjacent to the sidewall spacer regions. A barrier layer is provided between the first conduction layer and the second conduction layer and between the second conduction layer and the sidewall spacer regions.
Embodiments also include a semiconductor device including a field effect transistor, the field effect transistor including a gate dielectric layer, a gate electrode, sidewall spacers, a source region, and a drain region. The gate electrode includes a first conduction layer and a second conduction layer. The first conduction layer is formed on the gate dielectric layer. The second conduction layer is formed above the first conduction layer. The sidewall spacers are formed adjacent to side walls of the gate electrode. An insulation layer is provided adjacent to the sidewall spacers, wherein an upper surface of the insulation layer and an upper surface of the second conduction layer are substantially at the same level.


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U.S. application Ser. No. 09/963,168, filed Sep. 26, 2001, having U.S. patent Appl. Pub. No. US2002/0084476 A1, published on Jul. 4, 2002, and pending claims.
U.S. application Ser. No. 09/963,903, filed Sep. 26, 2001, having U.S. patent Appl. Pub. No. US2002/0117726 A1, published on Aug. 29, 2002.

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