Active solid-state devices (e.g. – transistors – solid-state diode – Non-single crystal – or recrystallized – semiconductor... – Field effect device in non-single crystal – or...
Reexamination Certificate
2002-07-31
2004-08-31
Tran, Thien F (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Non-single crystal, or recrystallized, semiconductor...
Field effect device in non-single crystal, or...
C257S072000, C257S075000, C257S347000
Reexamination Certificate
active
06784456
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a field effect transistor with an improved gate overlap drain structure and a method of manufacturing the same by utilizing a laser beam irradiation technique as well as a liquid crystal display using the same and a method of manufacturing the same.
All of patents, patent applications, patent publications, scientific articles and the like, which will hereinafter be cited or identified in the present application, will, hereby, be incorporated by references in their entirety in order to describe more fully the state of the art, to which the present invention pertains.
2. Description of the Related Art
In recent years, shrinkage of the semiconductor device causes shortening a gate width of a field effect transistor. The shortened gate width may cause short channel effects, and hot carrier injections, thereby resulting in deterioration of reliability of the field effect transistor. The short channel effects and the hot carrier injections may cause an extensively high field in the vicinity of the drain region of the transistor. In order to avoid the above undesired problems, it is effective to reduce or relax an extensively high field in the vicinity of the drain region of the transistor. In order to reduce or relax an extensively high field, a lightly doped drain (LLD) structure is effective, which has been known in the art, to which the present invention pertains. In accordance with the lightly doped drain (LLD) structure, off-set gate layers having lower impurity concentration are selectively formed in selected substrate regions between source/drain regions and a channel region under a gate electrode. The off-set gate layers contribute to relax undesired extensively high fields in the selected substrate regions between the source/drain regions and the channel region under the gate electrode. The off-set gate layers thus contribute to increase the withstand voltages, for example, a punch-through voltage and a hot carrier withstand voltage.
A method of forming a typical example of a conventional lightly doped drain structure will be described with reference to
FIGS. 1A through 1C
.
As shown in
FIG. 1A
, an isolation oxide film
14
is selectively formed over a silicon substrate
13
by a local oxidation of silicon method, thereby to define a field region which is surrounded by the isolation oxide film
14
. A gate oxide film
4
is formed on the field region by a thermal oxidation. A polysilicon film is then deposited by a low pressure chemical vapor deposition method over the gate oxide film
4
and the isolation oxide film
14
. A photo-lithography and a subsequent dry etching process are then carried out to form a gate electrode
5
. A first ion-implantation is then carried out at a low impurity concentration by use of the gate electrode
5
and the isolation oxide film
14
as masks for subsequent anneal under predetermined conditions to form low impurity concentration regions
16
.
As shown in
FIG. 1B
, a silicon oxide film is deposited by a low pressure chemical vapor deposition method over the gate electrode
5
and the isolation oxide film
14
as well as the low impurity concentration regions
16
. An anisotropic etching such as a dry etching is then carried out to etch-back the silicon oxide film, thereby to selectively form side wall oxide films
17
on opposite side walls of the gate electrode
5
.
As shown in
FIG. 1C
, a second ion-implantation is carried out at a high impurity concentration by use of the gate electrode
5
, the side wall oxide films
17
and the isolation oxide film
14
as masks for subsequent anneal under predetermined conditions to form high impurity concentration regions
18
, while the low impurity concentration regions
16
remain only under the side wall oxide films
17
, wherein boundaries between the high impurity concentration regions
18
and the low impurity concentration regions
16
are self-aligned to the outside edges of the side wall oxide films
17
. The high impurity concentration regions
18
serve as source and drain regions, while the remaining low impurity concentration regions
16
under the side wall oxide films
17
serve as the off-set gate layers.
The above lightly doped drain structure is, indeed, effective to relax the expensively high field concentration. Further high degree of shrinkage of the semiconductor device causes a further high degree of shortening the gate width which defines the channel width, namely of shortening the channel width. Increase in the degree of shortening the channel width may cause an undesired phenomenon that hot carriers generated in the vicinity of the drain region are trapped into side regions of the gate oxide film in the vicinity of the lightly doped drain regions or the low impurity concentration regions
16
. The trapped hot carriers may cause an undesired inversion in the conductivity type of the lightly doped drain regions
16
. The inversion in the conductivity type of the lightly doped drain regions
16
may cause an undesired variation in threshold voltage of the transistor and also an undesired drop of the punch-through withstand voltage.
In the meantime, it has been known in the art, to which the present invention pertains, a thin film transistor as typical one of the field effect transistors is used as a switching device for a liquid crystal display. In accordance with a basic structure of a polycrystal silicon thin film transistor used as a pixel switching transistor in the liquid crystal display, the lightly doped drain structure is effective to suppress or reduce a leakage of current, which may be a dark current. This lightly doped drain structure and the channel region of the polycrystal silicon thin film transistor have an disadvantage in possible increase in leakage of current or dark current upon incidence of light into the channel region, namely an off-leak current upon incidence of light into the channel region.
In order to reduce such undesired off-leak current upon incidence of light into the channel region, a pair of top and bottom light shielding layers is provided, wherein the top light shielding layer overlies the transistor, while the bottom light shielding layer underlies the transistor. As described above, in accordance with the lightly doped drain structure, the low impurity concentration regions are not covered by the gate electrode. This structure allows a light reflected by respective layers in an active matrix substrate of the display to become incident into the low impurity concentration regions, even the top and bottom optical shielding layers are provided. Namely, it is difficult to avoid the undesirable leakage of light or possible incidence of light into the low impurity concentration regions unless the low impurity concentration regions are completely covered by the gate electrode. This problem will be remarkable in a light valve active matrix liquid crystal display for liquid crystal light projection.
In order to have attempted to solve the above problems with the undesired possible trap of the hot carriers into the gate oxide film and with the undesired possible light incidence into the low impurity concentration regions, a gate-overlap-drain structure was proposed, wherein laminations of a gate insulation film and a gate electrode extend over the lightly doped drain structure, or over the low impurity concentration regions. This gate-overlap-drain structure is disclosed in Japanese laid-open patent publications Nos. 8-153875 and 8-222736. This gate-overlap-drain structure will be described.
FIGS. 2A through 2D
are fragmentary cross sectional elevation views of field effect transistors in sequential steps involved in a typical example of a conventional method of forming a gate-overlap-drain structure.
As shown in
FIG. 2A
, an isolation oxide film
14
is selectively formed over a silicon substrate
13
by a local oxidation of silicon method, thereby to define a field region which is surrounded by the isolation oxide film
14
. A gate oxide film
4
is form
NEC Corporation
Tran Thien F
Young & Thompson
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