Miscellaneous active electrical nonlinear devices – circuits – and – Specific identifiable device – circuit – or system – With specific source of supply or bias voltage
Reexamination Certificate
2002-11-25
2004-06-22
Lam, Tuan T. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Specific identifiable device, circuit, or system
With specific source of supply or bias voltage
C327S535000, C327S543000
Reexamination Certificate
active
06753720
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor circuit device, and more particularly, it relates to the structure of a circuit generating an internal voltage of a prescribed voltage level in its interior. More specifically, the present invention relates to the structure of a boosted voltage generation circuit generating a boosted voltage of a voltage level higher than that of an operating power supply voltage in a semiconductor memory device.
2. Description of the Prior Art
FIG. 53
schematically illustrates the structure of a conventional semiconductor circuit device CH. Referring to
FIG. 53
, the semiconductor circuit device CH includes a Vpp generation circuit PG generating a high voltage Vpp of a constant voltage level higher than that of an externally supplied power supply voltage VCC using this power supply voltage VCC, and an internal circuit NK performing a prescribed operation using the high voltage Vpp and the power supply voltage VCC. The internal circuit NK includes a Vpp utilization circuit NKa utilizing the high voltage Vpp from the Vpp generation circuit PG.
When the density and the degree of integration of a semiconductor circuit device including a MOS transistor (insulated gate field effect transistor) are enhanced, the size of the MOS transistor is refined. In order to ensure the reliability of a gate insulation film of the refined MOS transistor, it is necessary to prevent application of an excessive high voltage to the MOS transistor. Therefore, the voltage level of the power supply voltage VCC is reduced as the degree of integration and the density of the semiconductor circuit device are enhanced. Further, a high-speed operation is attained by reducing a signal amplitude, and current consumption is reduced by reducing a charge/discharge current for a signal line.
The semiconductor circuit device having such a refined MOS transistor utilizes the high voltage Vpp of a higher voltage level than the power supply voltage VCC for the following reason.
FIG. 54
illustrates a voltage application manner for an n-channel MOS transistor NQ included in the conventional semiconductor circuit device. Referring to
FIG. 54
, the n-channel MOS transistor NQ is supplied on its gate CG with a voltage changing between the high voltage Vpp and a ground voltage GND (0 V). An input signal IN changes between the power supply voltage VCC and the ground voltage GND (0 V). When the n-channel MOS transistor NQ has a threshold voltage Vth, it is possible to transmit a voltage (gate voltage V (CG)−Vth) from its source to its drain. When the high voltage Vpp is set at a voltage level exceeding the voltage VCC+Vth, therefore, an output signal OUT changing between the power supply voltage VCC and the ground voltage GND (0 V) can be obtained with no threshold voltage loss across the MOS transistor NQ.
High voltage Vpp is utilized for n-channel MOS transistor NQ in order to prevent the problem of threshold voltage loss thereby reliably transmitting a signal of the amplitude of the power supply voltage VCC. Thus, an internal signal of a desired amplitude can be correctly transmitted even if the power supply voltage VCC is at a low voltage level. Influence by such threshold voltage loss most remarkably appears on data read from a memory cell when this semiconductor circuit device is a semiconductor memory device.
FIG. 55
illustrates the structure of a memory cell MC of a conventional semiconductor memory device. Referring to
FIG. 55
, the memory cell MC is arranged in correspondence to a crossing between a word line WL and a bit line BL. The memory cell MC includes a capacitor Cm for storing information and an access transistor Qm conducting in response to a signal potential on the word line WL for connecting the capacitor Cm with the bit line BL. The access transistor Qm is formed by an n-channel MOS transistor. Such memory cells MC are arrayed in rows and columns, so that a row of memory cells MC are arranged in correspondence to the word line WL and a column of memory cells MC are arranged in correspondence to bit lines BL and /BL. In the example shown in
FIG. 55
, no memory cell MC is arranged at a crossing between the word line WL and the bit line /BL.
The bit lines BL and /BL are precharged at an intermediate voltage level. When the word line WL is selected, the access transistor Qm conducts so that the potential of the bit line BL changes in accordance with charges stored in the capacitor Cm. A sense amplifier (not shown) differentially amplifies and latches the potential difference between the bit lines BL and /BL. When the capacitor Cm stores high-level data, the bit line BL is driven to a power supply voltage Vcca (array power supply voltage) level. At this time, the word line WL is driven to a voltage level which is higher than the high-level voltage Vcca by the threshold voltage Vth of the access transistor Qm. Thus, the capacitor Cm stores data of the high-level voltage Vcca level with no influence by the threshold voltage Vth of the access transistor Qm.
The quantity of charges stored in a storage node (connection node between the access transistor Qm and the capacitor Cm) of the capacitor Cm is determined by the difference between the high-level data and a constant voltage (cell plate voltage) Vcp and the capacitance value of the capacitor Cm. Even if refinement (miniaturization) progresses to reduce the capacitance value of the capacitor Cm, therefore, it is possible to stably hold the high-level data by transmitting the voltage Vcca of the high-level data to the capacitor Cm with no threshold voltage loss thereby storing a sufficient quantity of charges. Also in data reading, it is possible to cause sufficient voltage difference (read voltage) on the bit line BL.
In the conventional semiconductor memory device (dynamic random access memory), therefore, the word line WL is generally driven to a voltage level higher than the power supply voltage Vcca supplied to a memory cell array. Therefore, a circuit driving the word line WL to the high voltage Vpp level utilizes the high voltage Vpp.
FIG. 56
shows another structure of the Vpp utilization circuit NKa. Referring to
FIG. 56
, an output circuit OB converts data D and /D read from an internal memory cell of a semiconductor memory device to external read data DQ and outputs the same. Referring to
FIG. 56
, the output circuit OB includes a level conversion circuit OBa converting the voltage level of the internal read data D to a high voltage Vpp level, an n-channel MOS transistor OBb conducting, when an output signal of the level conversion circuit OBa is at a high level, for driving the external data DQ to a power supply voltage VQ level, and an n-channel transistor OBc conducting when the complementary internal read data /D is at a high level, for setting the external read data DQ at the ground voltage level.
The power supply voltage VQ determines a high level of the external read data DQ. If the n-channel MOS transistor OBb causes threshold voltage loss when the voltage level of the power supply voltage VQ is lowered, the high level of the external read data DQ is so reduced that an external circuit receiving the read data DQ cannot correctly determine the high/low level. In order to eliminate the threshold voltage loss in the MOS transistor OBb, the level conversion circuit OBa generates a signal of the high voltage Vpp level in accordance with the internal read data D (level conversion of the internal read data). Thus, the output circuit OB outputs the read data DQ of the power supply voltage VQ level to an exterior, enabling correct data reading.
This structure including the n-channel MOS transistors OBb and OBc as MOS transistors for charging/discharging an output node in the output circuit OB shown in
FIG. 56
is widely employed in a highly integrated semiconductor memory device, in view of prevention of a latch-up phenomenon and reduction of an occupation area due to reduction of an area for P-N isolation.
FIG. 57
schematically illustrates the s
Furutani Kiyohiro
Kono Takashi
Mitsui Katsuyoshi
Lam Tuan T.
McDermott & Will & Emery
Nguyen Hiep
Renesas Technology Corp.
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