Memory cell of a semiconductor memory device

Details Memory cell of a semiconductor memory device Memory cell of a semiconductor memory device

1989-06-14

1990-09-25

Hille, Rolf

357 41, 357 45, H01L 2702, H01L 2978, H01L 2710

Patent

active

049596985

ABSTRACT:
A DRAM memory cell includes one transistor and one capacitor surrounded by an isolating region. A first electrode of the transistor is formed at the center of the memory cell in a major surface of a substrate. A gate electrode of the transistor is formed on the major surface of the substrate around the first electrode. The capacitor is formed around the gate electrode of the transistor, and may include, as one electrode thereof, a second electrode of the transistor. Various embodiments are described, some including formation of certain of the memory cell elements in a trench in the major surface of the substrate. As a result, current leakage is prevented, capacitor holding time is improved and transistor threshold voltage may be made more stable.

REFERENCES:
patent: 4151607 (1979-04-01), Koyanagi et al.
Nakamura, K., "Buried Isolation (BIC) Cell for Megabit MOS Dynamic RAM", IEDM 84, pp. 236-239.
Wada et al., "A Folded Capacitor Cell (FCC) for Future Megabit DRAM's", IEDM 84, pp. 244-247.

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