Printhead substrate inputting a data signal and a clock...

Details Printhead substrate inputting a data signal and a clock... Printhead substrate inputting a data signal and a clock...

2002-06-07

2004-06-01

Stephens, Juanita (Department: 2853)

Incremental printing of symbolic information

Ink jet

Ejector mechanism

C347S059000

Reexamination Certificate

active

06742874

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to a printhead substrate for inputting a data signal in synchronization with a clock signal, printhead, printhead cartridge, and printer thereof.
BACKGROUND OF THE INVENTION
FIGS. 1 and 2
show respectively a layout and a circuit diagram of a conventional inkjet printhead for inputting a data signal in synchronization with a clock signal.
Referring to
FIG. 1
, a printhead substrate (heater board)
100
includes: a heater portion
101
serving as an electrothermal transducer; a driver portion
102
having a transistor for driving the heater portion
101
; a latch
103
latching printing data; a shift register
104
storing serially inputted printing data; and a PAD portion
105
serving as an input terminal where various signals are inputted.
FIG. 2
is a circuit diagram of the heater board
100
shown in FIG.
1
. Components common to those shown in
FIG. 1
are referred to by the same reference numerals. The heater portion
101
includes a plurality of heaters (resisters) and the driver portion
102
has an FET transistor, a buffer circuit for each heater.
FIG. 3
is a view explaining a relation between input waveforms, obtained when the CLK signal and DATA signal driving the circuit shown in
FIG. 2
are inputted to the heater board
100
, and input waveforms obtained when the CLK signal and DATA signal are inputted to the points A and B of the shift register
104
.
Assume herein that the DATA signal is inputted to the shift register
104
in synchronism with two transitional states (leading and trailing edge) of CLK signals, i.e., a state changing from a low level to a high level, and a state changing from a high level to a low level. Note that the DATA signal, sent from a printer main unit employing the printhead, is a high-level or low-level signal for turning on/off a desired heater (heating element). The DATA signal inputted to the PAD portion
105
is sent to the Schmitt circuit
106
, then through the buffer circuit
107
connected to the output terminal of the Schmitt circuit
106
, inputted to the shift register
104
(point B). Similarly, the CLK signal from the PAD portion
105
is inputted to the Schmitt circuit
106
, then through the buffer circuit
107
connected to the output terminal of the Schmitt circuit
106
, inputted to the shift register
104
(point A). The DATA signal is inputted to the shift register
104
in synchronization with both transitions of a low level to a high level and a high level to a low level of the CLK signal.
In a case where the number of shift registers
104
provided is one as in a conventional printhead, the number of logic gates from the PAD portion
105
to the shift register
104
is equal in the CLK signal and DATA signal. Furthermore, a load driven by each of the buffer circuits
107
is equal in the CLK signal and DATA signal. Therefore, the time lag of the CLK signal generated between the PAD portion
105
and the point A is equal to the time lag of the DATA signal generated between the PAD portion
105
and the point B. Thus, the temporal relative relation between the CLK signal and DATA signal is equal in the PAD portion
105
and the input portions A and B of the shift register
104
. In order to surely input the DATA signal to the shift register
104
without malfunction, the level of the DATA signal needs to be constant before and after the transition of the CLK signal. In other words, the time during which the DATA signal is constant with respect to the CLK signal, i.e., setup time and hold time, must be equal in the input portions A and B of the shift register
104
so as to allow a margin for malfunction and enable high-speed data transfer.
In order to meet the recent demands for high-precision printing quality of a color image, for instance as shown in
FIG. 4
, a single heater board (head substrate) comprises plural heating elements (heaters) for printing images in plural colors. Furthermore, in keeping with the trend of increasing speed and higher precision in printing, a discharge frequency of the heaters is increased with increasing of the number of heaters. As a result, the amount of data transferred to the printhead per unit time increases. In order to handle the increased amount of data, the transferred data is divided, and the divided plural blocks of data are transferred simultaneously in synchronization with one clock signal. In this case, a plurality of shift registers need to be provided in the printhead in conformity to the plural blocks of data.
In the printhead having a plurality of shift registers, in order to simultaneously input the DATA signal to the plurality of shift registers in synchronization with the clock signal, it is necessary to input a number of CLK signals and DATA signals corresponding to the number of shift registers. However, if a plurality of pads for inputting these signals and corresponding input circuits are provided in the printhead substrate, the layout area necessary for these circuits increases, and as a result, the chip size increases. Furthermore, since the aforementioned substrate is formed on a silicon wafer, the increased chip size causes a decreased number of chips produced from one sheet of wafer, resulting in an increased cost.
In order to avoid the increased chip size, it is necessary to reduce the number of signal lines inputted to the heater board. To realize this, the CLK signal serving as a common synchronization signal for the plural shift registers
401
to
406
is provided as a common signal so that, for instance, only one input pad is necessary for the CLK signal as shown in FIG.
5
. In this case, while plural shift registers
401
to
406
are connected to the output of the buffer circuit
500
of the CLK signal, only one shift register is connected to each output of the buffer circuit
501
of the DATA signal. Assuming that a current driving capability of the buffer circuit
500
is equal to that of the buffer circuit
501
, a difference is generated between a time lag of the CLK signal and a time lag of the DATA signal inputted to each shift register. More specifically, there is more delay in the CLK signal than the DATA signal. When a power-supply voltage is 5V as in a conventional case, the time lag of the signal is small since the current driving capability of the buffer circuit
500
is sufficient. Therefore, the difference between the time lag of the CLK signal and the time lag of the DATA signal is small in each shift register.
For an interface of a conventional printer, a parallel interface has been employed in general. In this case, a power-supply voltage used for the logic of the printer main unit is 5V. Also, a power-supply voltage for the logic of an inkjet printhead substrate in the head is 5V. Furthermore, a part of an IC of the printer's internal circuit requires a 5V power supply. These are the background of the feature of the inkjet printhead substrate, which has been developed to use a 5V logic power supply.
However, recently as the microtechnology of an IC design rule has improved and a new interface has been employed, adopting a 5V logic power supply is disadvantageous in terms of cost and size. In view of this, adopting 3.3V is the recent movement in the mainstream of a logic power supply of a printer main unit. However, it has been confirmed that several problems occur if a logic power-supply voltage in a head substrate is lowered from the time-proven 5V to 3.3V. The problems are described below with reference to drawings.
One of the problems is reduced image data transfer capability of an inkjet printhead substrate.
FIG. 18
shows an example of a construction of an inkjet printhead substrate. Reference numeral
1003
denotes a pad receiving a signal from an external unit. A VDD terminal
1006
receives a logic power-supply voltage, a VH terminal
1008
receiving a heater driving power-supply voltage, a GND terminal
1005
connected to a ground, and a VSS terminal
1007
. Furthermore, a logic circuit
1002
, such as a shift register, which serially receives image data an

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