Semiconductor memory device

Details Semiconductor memory device Semiconductor memory device

2003-01-14

2004-10-19

Lam, David (Department: 2818)

Static information storage and retrieval

Floating gate

Particular biasing

C365S185230, C365S185180

Reexamination Certificate

active

06807099

ABSTRACT:

CROSS REFERENCE TO RELATED APPLICATION
This application claims benefit of priority under 35 U.S.C. §119 to Japanese Patent Application No. 2002-6847, filed on Jan. 16, 2002, the entire contents of which are incorporated by reference herein.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to an electrically programmable semiconductor memory device, and particularly relates to a semiconductor memory device in which a program control operation is performed.
2. Description of the Related Art
As shown in
FIG. 11
, a related semiconductor memory device includes a block decoder
10
, voltage supply circuit CG drivers
6
, a VPP pump circuit
30
, a VPASS pump circuit
40
, and a VRDEC driver
150
. The VRDEC driver
150
shown in
FIG. 12
has NMOS D-type transistors
152
connected in series, and a voltage VPGMH is inputted to gates of the transistors
152
via a level shifter
151
. A voltage VPGMH is inputted to their one end, and a control signal VRDEC is outputted from the other end side. Moreover, NMOS D-type transistors
154
connected in series are provided between the control signal VRDEC and a voltage VDD, and a control signal VRDEC_V is inputted to gates of the transistors
154
via an inverter
153
.
A memory region includes, for example, NAND-type flash memory cells. In
FIG. 11
, a top-bottom direction is a row direction, and a left-right direction is a column direction. The number of memory cells in the row and column directions is set properly according to memory capacity.
FIG. 13
shows the voltages of some nodes in this semiconductor memory device as program operation waveforms. At a time t
0
, a block is selected by an inputted address, and the VRDEC driver
150
outputs the voltage VPGMH to the row decoder in response to the control signal VRDEC_V. Namely, when the signal VRDEC_V goes to the voltage VDD at the time t
0
, an output of the control signal VRDEC starts to rise from the voltage VDD to the voltage VPGMH, that is, 20 V+Vtn. Program data is outputted to bit lines BL
0
to BLi from a sense amplifier
50
, a selection gate SGD (SG
2
) on the bit line side is driven to the voltage VDD, and the program data is inputted to the selected NAND-type cell.
If a program voltage VPGM and a program intermediate voltage VPASS are transferred from the voltage supply circuit CG drivers
6
to their respective word lines CG
0
to CG
15
at a time t
1
, a program operation is executed by the program data sent from the bit lines BL
0
to BLi. In this case, the program intermediate voltage VPASS (10 V in
FIG. 13
) is used not only to turn on memory cells (non-selected cells) in the non-selected word lines between the selection gate and the selected memory cell and transfer the program data from the bit line to the selected memory cell but also to generate a non-program voltage in channels in the NAND cell so as not to bring about a threshold voltage shift to the selected memory cell.
Incidentally, in a circuit configuration shown in
FIG. 11
, when the supply of the voltage VPGM starts at the time t
1
, the level of the voltage VPGMH for transferring the program voltage VPGM by transfer transistors
3
is lowered by parasitic capacitance of a path for transferring the voltage VPGM and word line capacitance. As the capability of the VPP pump circuit
30
is lower and the load of the VPGM transfer path is larger, this tendency becomes stronger. On this occasion, the voltage VPGM is generated so as to become a voltage lower than the voltage VPGMH by a threshold voltage of an NMOS transistor
25
at an output part of the VPP PUMP
30
, and hence it operates together while having at least a difference Vtn corresponding to the threshold voltage of the NMOS transistor
25
. Accordingly, when a voltage with the same voltage as the voltage VPGMH is transferred to gates Transfer G of the transfer transistors
3
in the selected row decoder, as shown by (A) in
FIG. 13
, a voltage of 20 V+Vtn is transferred to the gates Transfer G of the transfer transistors
3
, whereby 20 V can be transferred to the selected word line.
Next,
FIG. 14
shows the circuit configuration of a level shifter
2
in the block row decoder
10
. A D-type NMOS transistor
90
is provided, and the control signal VRDEC of 20 V+&agr; is inputted to a source of the transistor
90
. The gates Transfer G of the transfer transistors
3
are connected to a gate of this NMOS transistor
90
. A PMOS transistor
91
is connected to a drain of the D-type NMOS transistor
90
, and an output
2
of a decoder is connected to a gate of the transistor
91
. An NMOS transistor
92
is connected to a drain of the PMOS transistor
91
, and the voltage VDD is inputted to a gate of the transistor
92
. An output
1
of the decoder is inputted to a source of the NMOS transistor
92
.
When the block decoder including this level shifter is selected, the output
1
of the decoder becomes the voltage VDD, and the output
2
of the decoder becomes 0 V. Therefore, the NMOS transistor
92
is cut off after transferring a voltage VDD-Vtn to the gate Transfer G, the D-type NMOS transistor
90
transfers a voltage corresponding to the gate Transfer G to a well and a source of the PMOS transistor
91
, and then the PMOS transistor
91
is turned on. Consequently, the voltage transferred by the NMOS D-type transistor
90
is transferred to the gate Transfer G via the PMOS transistor
91
turned on. By this voltage, the NMOS D-type transistor
90
transfers a higher voltage. As stated above, positive feedback is given between Transfer G and the transistors
90
and
91
, whereby the voltage to be applied to VRDEC is applied as shown by an arrow in FIG.
14
.
In the aforementioned related semiconductor memory device, the following problems arise. Due to a problem in terms of an operation margin, a case where the voltage of VPGMH cannot be fully transferred to the gates Transfer G of the transfer transistors
3
as shown in a waveform C
1
in
FIG. 13
may occur.
The relation between the threshold voltage of the NMOS D-type transistor
90
and current amount in the level shifter
2
is shown now in FIG.
15
. As the voltage is applied to its source, the threshold voltage becomes larger by back gate bias effect. When back gate bias characteristics greatly deteriorate for some reason as in a case
2
although characteristics of a case
1
is assumed at the time of the application of a back gate bias of 20 V+Vtn at the beginning of a circuit design, that is, it is assumed that the NMOS D-type transistor is in an ON state until it transfers VPGMH, the voltage shown in
FIG. 14
which the level shifter can transfer lowers greatly.
On this occasion, in terms of a DC operation, after the level shifter is charged to a voltage such as shown by a waveform C
1
shown by a broken line in
FIG. 13
, the gates Transfer G of the transfer transistors
3
become floating. When the voltage of the voltage VPGMH to which the control signal VRDEC is charged lowers as stated above since the program voltage VPGM (20 V) is transferred to the word line at the time t
1
, the voltage of the gates Transfer G of the transfer transistors
3
lowers concurrently therewith, and the gates Transfer G of the transfer transistors
3
are biased in terms of DC until a time tf. Since the gates Transfer G of the transfer transistors
3
become floating after the time tf, the voltage of the gates Transfer G of the transfer transistors
3
slightly rises by coupling effect even after the time tf by contribution of the program voltage VPGM and the program intermediate voltage PASS in the middle of activation, and a waveform C
2
is obtained. The voltage of the waveform C
2
is higher than the voltage of the waveform C
1
, but unless it rises to 20 V+Vtn which is the voltage of VPGMH, the voltage to be transferred to the selected word line becomes a low voltage shown by the waveform C
2
, and hence the predetermined voltage VPGM (20 V) cannot be transferred. Namely, the program voltage VPGM cannot be completely transferred.
In

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