Active solid-state devices (e.g. – transistors – solid-state diode – Integrated circuit structure with electrically isolated... – Including dielectric isolation means
Reexamination Certificate
2002-11-19
2004-11-02
Jackson, Jerome (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Integrated circuit structure with electrically isolated...
Including dielectric isolation means
C257S052000, C257S524000, C257S508000, C257S506000
Reexamination Certificate
active
06812540
ABSTRACT:
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a semiconductor integrated circuit device. More particularly, the present invention relates to a technology effectively applied to a semiconductor integrated circuit device provided with a high-density integrated memory circuit, a logic embedded DRAM in which a memory circuit and a logic circuit are provided on the same semiconductor substrate, and an analog circuit, which use a MISFET pair formed by the use of device isolation trenches.
BACKGROUND OF THE INVENTION
For example, a device isolation trench is used for the isolation of MISFETs in a logic embedded memory in which a DRAM (Dynamic Random Access Memory) and a logic circuit composed of a MISFET (Metal Insulator Semiconductor Field Effect Transistor) and the like are provided on the same semiconductor substrate. Note that a device relative to this type of device is disclosed in the gazette of Japanese Patent Laid-Open No. 2000-174225.
SUMMARY OF THE INVENTION
In the device isolation technique using the device isolation trench for isolating the devices, the shape of a device isolation trench is changed depending on the degree of density of the device isolation trench areas and the device active areas, more specifically, depending on the width of the device isolation trench.
As a result, there arises a problem of the threshold voltage difference between the MISFET pair used in a sense amplifier circuit in which constant electric characteristics are required.
An object of the present invention is to provide a technique capable of improving the characteristics of a MISFET, in which constant electric characteristics are required, in a semiconductor integrated circuit device provided with a DRAM, a logic embedded memory, and an analog circuit, which use device isolation trenches. In particular, the object is to provide a technique capable of improving the characteristics of a MISFET pair that constitutes a sense amplifier circuit.
Another object of the present invention is to achieve a high performance of a semiconductor integrated circuit device.
Another object of the present invention is to achieve high integration of a semiconductor integrated circuit device.
The above and other objects and novel characteristics of the present invention will be apparent from the description and the accompanying drawings of this specification.
The typical ones of the inventions disclosed in this application will be briefly described as follows.
The device isolation trenches that contact to the edges of an active area on which gate electrodes of a MISFET pair are arranged are designed to have the same width. Alternatively, the width difference between the trenches is reduced to be smaller than twice the minimum processing dimension. As a result, the shapes of the device isolation trenches determined in accordance with the widths thereof are almost equal to each other, and thus, the threshold voltage difference in the MISFET pair caused from the difference in shape of the device isolation trenches is reduced. Therefore, the performance of a sense amplifier comprised of the MISFET is improved and the refresh characteristics of a DRAM memory cell can be improved.
Also, the threshold voltage difference caused from the difference in shape of the device isolation trenches is particularly large in a p-channel MISFET. Therefore, if only the width difference between the device isolation trenches that contact to the edges of the active area over which the p-channel MISFET pair is arranged is reduced to almost zero or to be smaller than twice the minimum processing dimension, the high integration in the active area of the n-channel MISFET pair can be achieved, and the threshold voltage difference between the p-channel MISFET pair caused from the difference in shape of the device isolation trenches can be reduced.
In addition, in a sense amplifier circuit in which a plurality of active areas, each having a MISFET pair arranged thereon, are successively arranged, if the width difference between the device isolation trenches that contact to the edges of the active area over which the MISFET pair is arranged is reduced to almost zero or to be smaller than twice the minimum processing dimension, the sense amplifier pitch can be expanded more than twice, and the threshold voltage difference between the n-channel MISFET pair caused from the difference in shape of the device isolation trenches can be reduced.
In addition, in the sense amplifier circuit in which a plurality of active areas, each having a p-channel MISFET pair arranged thereon, are successively arranged, if only the width difference between the device isolation trenches that contact to the edges of the active area over which the p-channel MISFET pair is arranged is reduced to almost zero or to be smaller than twice the minimum processing dimension, the sense amplifier pitch can be expanded more than twice, and the high integration in the active area of the n-channel MISFET pair can be achieved, and further, the threshold voltage difference between the p-channel MISFET pair caused from the difference in shape of the device isolation trenches can be reduced.
In addition, in a sense amplifier circuit in which a plurality of active areas, each having a MISFET pair arranged thereon, are successively arranged, for example, p-well active areas are used as active areas closest to the active area of the n-channel MISFET pair and n-well active areas (n-type active area) are used as active areas closest to the active area of the p-channel MISFET pair, whereby the difference between the length between the active areas each having a p-channel MISFET pair arranged thereon and the length between the active areas each having an n-channel MISFET pair arranged thereon can be reduced to almost zero or to be smaller than twice the minimum processing dimension. As a result, the threshold voltage difference in the MISFET pair can be reduced.
In addition, in a sense amplifier circuit in which a plurality of active areas, each having a MISFET pair arranged thereon, are successively arranged, for example, a p-well active area is used as either or both of the active areas closest to the active area of the p-channel MISFET pair, and the length between the active areas over which the p-channel MISFET pair is arranged is set larger than that between the active areas over which the n-channel MISFET pair is arranged, thereby making it possible to reduce the threshold voltage difference in the MISFET pairs.
Also, in a sense amplifier circuit in which a plurality of active areas each having a MISFET pair arranged thereon are arranged separately from each other, a p-well active area over which an n-channel MISFET pair is arranged is arranged between the n-well active areas over which a p-channel MISFET pair is arranged, thereby isolating the p-well active area of the memory cell from the p-well active area on which an n-channel MISFET pair is arranged. By doing so, it is possible to electrically isolate the p-well active area of the memory cell from the p-well active area over which an n-channel MISFET pair is arranged. As a result, it is possible to promote the high speed driving of the sense amplifier.
Also, in a sense amplifier circuit in which a plurality of active areas each having a MISFET pair arranged thereon are arranged separately from each other, a p-well active area over which an n-channel MISFET pair is arranged is arranged between the n-well active areas over which a p-channel MISFET pair is arranged, thereby isolating the p-well active area of the memory cell from the p-well active area over which an n-channel MISFET pair is arranged, and the width difference between the device isolation trenches that contact to the edges of the active area over which gate electrodes of the MISFET pair are arranged is reduced to almost zero or to be smaller than twice the minimum processing dimension. By doing so, it is possible to electrically isolate the p-well active area of the memory cell from the p-well active area over which an n-channel MISFET pair is arran
Asakura Hisao
Kimura Shin'ichiro
Matsuoka Hideyuki
Nagai Ryo
Takaura Norikatsu
A. Marquez, Esq. Juan Carlos
Fisher Esq. Stanley P.
Hitachi , Ltd.
Jackson Jerome
Nguyen Joseph
LandOfFree
Semiconductor integrated circuit device does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Semiconductor integrated circuit device, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor integrated circuit device will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3317219