Semiconductor memory decoder device

Details Semiconductor memory decoder device Semiconductor memory decoder device

1996-10-24

1998-01-13

Zarabian, A.

Static information storage and retrieval

Addressing

Sync/clocking

36523006, 36523003, 36523004, G11C 700

Patent

active

057086230

ABSTRACT:
A memory device comprising a cell array including first and second cell array blocks for storing data therein, a first row address buffer for generating a first internal row address signal in response to an external row address signal and a first row address strobe signal, a second row address buffer for generating a second internal row address signal in response to the external row address signal and a second row address strobe signal, a first pre-decoder for pre-decoding the first internal row address signal from the first row address buffer, a second pre-decoder for pre-decoding the second internal row address signal from the second row address buffer, a first row decoder for selectively driving word lines in the first cell array block in response to the pre-decoded first internal row address signal from the first pre-decoder, and a second row decoder for selectively driving word lines in the second cell array block in response to the pre-decoded second internal row address signal from the second pre-decoder. The memory device further comprises a row address strobe bar buffer for generating the first and second row address strobe signals in response to an external row address strobe bar signal, a column address strobe bar signal, a write enable signal, an output enable signal and a mode enable signal.

REFERENCES:
patent: 4758992 (1988-07-01), Taguchi
patent: 5241510 (1993-08-01), Kobayashi
patent: 5257233 (1993-10-01), Schafer
patent: 5392239 (1995-02-01), Margulis et al.
patent: 5613094 (1997-03-01), Khan

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