Data processing: measuring – calibrating – or testing – Testing system – Of circuit
Reexamination Certificate
2001-10-19
2004-10-05
Assouad, Patrick J. (Department: 2857)
Data processing: measuring, calibrating, or testing
Testing system
Of circuit
C714S718000
Reexamination Certificate
active
06801869
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Technical Field
The present invention relates in general to testing electronic devices and, in particular, to testing integrated circuits. Still more particularly, the present invention relates to a method and system for wafer and device-level testing of integrated circuits such as logic devices.
2. Description of the Related Art
Integrated electronic circuits, such as logic devices, are often designed to use external devices, such as dynamic random access memories (DRAMs), to provide data storage in electronic systems, such as computer systems. To ensure proper operation of the electronic systems, the manufacturing process for integrated circuit logic devices includes a number of testing steps intended to verify that the logic devices will provide reliable performance over the expected lifetime of the electronic systems in which they are installed.
A typical manufacturing process for logic devices begins with the fabrication of a semiconductor wafer containing hundreds or even thousands of identical dice. The circuitry in each logic device using external DRAM generally includes integrated DRAM interface circuits for storing data into and retrieving data from the DRAM's memory array and performing other operations in response to memory requests or commands.
Following wafer fabrication, a quick wafer probe is performed in an attempt to identify dies on the wafer having defects. The wafer probe often tests only a small portion of the circuits in the DRAM interface utilizing clock rates that are lower than normal operating frequencies.
Following the wafer probe, the wafer is scribed into dice. Dice marked as faulty after the wafer probes are discarded, and dice passing the wafer probe are packaged to obtain logic devices. Packaging technologies that are commonly used for logic devices include, among others, ball grid array (BGA) and wire bond.
After packaging, the logic devices are subjected to device-level testing. Device-level testing, like the wafer probe tests, may include low frequency tests of the DRAM interface circuits. Device-level testing may also include a “burn-in” test in which the packaged logic devices under test are subjected to high ambient temperatures and tests of long duration in order to discover early life failures. Device-level testing also differs is from wafer probe testing in that, in addition to basic pattern testing of the DRAM interface circuits, device-level testing generally tests the DC and AC characteristics of the logic and operation of the memory interface. Device-level testing also differs from wafer probe testing in that device-level testing is typically performed at or near the rated signal frequencies of the external DRAM, and these frequencies often require more sophisticated and expensive test equipment.
Logic devices with DRAM interface circuitry that pass the device-level test may subsequently be assembled onto circuit cards to form logic boards such as computer main boards and Peripheral Component Interconnect (PCI) expansion boards. Each logic board is then typically subjected to a final, intensive fault test prior to shipping or installation. The faults detected by board testing include faults in the circuit cards themselves (e.g., open or shorted traces), faults introduced by board assembly (e.g., damaged pin drivers, open or shorted pins, and ESD damage), and undetected faults in the logic device circuitry. Following completion of testing, logic devices and boards that pass can then be installed in an end-use application.
One drawback of the conventional logic device manufacturing process outlined above is that a number of faults are not discovered until late in the manufacturing process, for example, during device-level and board testing. As appreciated by the present invention, if such defects could be detected earlier in the manufacturing process (i.e., during wafer testing), the significant expense associated with packaging and board assembly of the defective dice could be eliminated. Unfortunately, the expense of the sophisticated test equipment currently required to fully exercise integrated DRAM interface circuitry prohibits its use during wafer testing.
A second drawback of the conventional manufacturing process is that several different pieces of specialized test equipment are required to fully test many integrated circuit logic devices. For example, to test the DRAM interface of a logic device, an algorithmic tester is utilized to stress the AC timing of a predetermined parameter for memory accesses. A separate vector tester is utilized to exercise the built-in self-test (BIST) functions of the logic device. A third system tester is often employed to verify proper operation of external DRAM in response to commands. As will be appreciated, the use of multiple testers compounds the expense of testing.
A third drawback of the prior art is that conventional test equipment does not fully emulate the intended end-use environment of devices under test. In particular, conventional testers for packaged logic devices and boards have a fixed input impedance. This input impedance cannot be adjusted and may result in test behavior that is quite different from the operating behavior of the logic with DRAM interface device under test when it is eventually installed in an end-use environment. Consequently, there may be an unacceptably high number of faulty devices or boards that pass the test process and even some satisfactory devices that fail the test process.
SUMMARY OF THE INVENTION
The present invention overcomes the foregoing and additional shortcomings in the prior art by introducing an improved method and system for wafer and device-level testing of integrated circuits such as logic devices with DRAM interface circuits.
According to a preferred embodiment of the present invention, a tester comprises test logic and a connector for at least one device under test. The connector, which may comprise a wafer probe for dice on a wafer or a test fixture for packaged integrated circuit devices, has connections for the device under test that present an impedance selected to emulate the characteristic impedance of an end-use environment of the device under test. For example, in an embodiment in which the device under test comprises logic devices using Rambus™ Signal Levels to interface to memory and the end-use environment is a Rambus™ channel connecting to Rambus DRAMs (RDRAMs), the characteristic impedance is between approximately 20 and 60 ohms. If, on the other hand, the end-use environment is connection to a socket for Rambus™ memory modules, then the characteristic impedance is approximately 28 ohms. Alternatively, if the end-use environment is connection to a socket for double data rate (DDR) memory modules, then the characteristic impedance is approximately 60 ohms. Thus, the tester of the present invention can accurately simulate operational behavior in an end-use environment of the device under test. Because this accurate simulation is available even for dice on a wafer, the needless expense associated with packaging defective dice and assembling defective dice onto boards can be avoided.
The test logic, which is coupled to the connector for communication with the device under test, transfers test commands and test data to the device under test. The test data and commands are utilized to perform multiples types of tests, including tests of the core logic and interface logic of the device under test. In this manner, the need for multiple types of testers is reduced or eliminated.
Additional objects, features, and advantages of the present invention will become apparent from the following detailed written description.
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Assouad Patrick J.
Dillon & Yudell LLP
Russell Brian F.
LandOfFree
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