Static information storage and retrieval – Floating gate – Particular biasing
Reexamination Certificate
2003-12-17
2004-10-05
Phan, Trong (Department: 2818)
Static information storage and retrieval
Floating gate
Particular biasing
C365S185240, C365S185270, C365S185290
Reexamination Certificate
active
06801456
ABSTRACT:
BACKGROUND OF INVENTION
1. Field of the Invention
The present invention relates to a method for operating a flash memory, more specifically, to a method for programming, erasing and reading a single-transistor P-channel flash memory.
2. Description of the Prior Art
For the past decade, technology and application of flash memory cells has gradually expanded with an increase of portable devices. Since portable devices usually use batteries as a power source, reduction in energy dissipation and operating the flash memory cell at optimum conditions are main areas of research in memory cell development. Generally, the flash memory cell is divided into a P-channel and an N-channel. The P-channel flash memory cell has characteristics of low power consumption, low programming voltage, and fast programming, so that the P-channel flash memory cell has been adapted to be used in a field of portable devices. Programming methods for the P-channel flash memory cell can be divided into three kinds: channel hot hole induced hot electron programming, band-to-band tunneling (BTBT), and Fowler-Nordheim (FN) tunneling.
In 1992, Hsu et al. in an article entitled “A High Speed, Low Power P-Channel Flash EEPROM Using Silicon Rich Oxide as Tunneling Dielectric”, International Conference on Solid State Devices and Materials (SSDM), 1992, pp.140-142, which is incorporated herein by reference, disclosed that by using silicon rich oxide (SRO) as tunneling dielectric in P-channel EEPROM cell, a high speed, low power and low voltage flash EEPROM can be accomplished. The hot electron injection in P-channel cell can be 2 orders in magnitude greater than that in N-channel cell, while the channel current during programming in P-channel cell is 2 orders in magnitude less than that in N-channel cell.
T. Ohnakado et al. in an article entitled “Novel Electron Injection Method Using Band-to-Band Tunneling Induced Hot Electron (BBHE) for Flash Memory with a P-channel Cell”, IEEE International Electron Devices Meeting Technical Digest, 1995, pp.279-282, disclosed a PMOS floating gate (FG) memory cell. A PMOS FG cell is formed in an N-well region of a P substrate. A P
+
source and a P
+
drain are formed in the N-well region. Dopants of the N typeare implanted into a channel region to realize an enhancement mode device. An N type polysilicon floating gate is insulated from the N-well region by a tunneling oxide layer. A control gate is insulated from the floating gate by another insulating layer. The cell is programmed by applying a high positive voltage of about 10 volts to the control gate, approximately −6 volts to the P
+
drain, floating the P
+
source, and grounding the N-well region. Under these bias conditions, hot electrons induced by band-to-band tunneling (BTBT) are injected into the floating gate. The resultant accumulation of charge on the floating gate increases the threshold voltage V
T
of the cell to approximately −2.5 volts. Thus, when programmed, the cell operates as an enhancement mode device.
Please refer to FIG.
1
.
FIG. 1
is a cross-sectional diagram of a prior art typical P-channel flash memory cell
10
′ in a programming mode. As shown in
FIG. 1
, the P-channel flash memory cell
10
′ is comprised of an N-type doped substrate
12
′, an N-type doped control gate
14
′, an N-type doped floating gate
16
′, a P
+
source
17
′, a P
+
drain
18
′, a tunneling oxide layer
21
′ located between the floating gate
16
′ and the substrate
12
′, and an oxide-nitride-oxide (ONO) dielectric layer
22
′ located between the control gate
14
′ and the floating gate
16
′.
In a general band-to-band tunneling (BTBT) programming mode, a positive high voltage of 10 volts is provided to the control gate
14
′, a negative voltage of −6 volts is provided to the drain
18
′, the substrate
12
′ in grounded, and the source
17
′ is in a floating state. In programming mode, electron-hole pairs are generated by band-to-band tunneling in a region where the drain
18
′ and the floating gate
16
′ overlap. The generated electrons are repelled into the channel region under the floating gate
16
′. Some electrons get enough energy to overcome an energy barrier of the tunneling oxide layer
21
′ and inject into the floating gat
16
′. Please note that programming efficiency and tunneling probability of electrons of the BTBT mechanism are related to an energy gap in the valance band-conduction band (EV-EC) in the region where the drain
18
′ and the floating gate
16
′ overlap. The smaller the energy gap is, the greater the band-to-band tunneling probability of electrons will be present.
SUMMARY OF INVENTION
It is a primary objective of the present invention to provide a low-voltage program, read and erase method for P-channel single-transistor flash memory cell.
According to the claimed invention, a method for programming a PMOS single-transistor memory unit is disclosed. The PMOS single-transistor memory unit is comprised of a silicon dioxide-silicon nitride-silicon dioxide (ONO) dielectric stack disposed on an N-well, a P type polysilicon gate disposed on the ONO dielectric stack, a P type doped source region disposed in the N-well at one side of the P type polysilicon gate, and a P type doped drain region disposed in the N-well on the other side of the P type polysilicon gate. The method comprises: biasing said P type polysilicon gate of said PMOS single-transistor memory unit to a word line voltage V
WL
; biasing said P type doped source region of said PMOS single-transistor memory unit to a source line voltage V
SL
that is greater than the word line voltage V
WL
, wherein |V
WL
−V
SL
| is larger than threshold voltage of said PMOS single-transistor memory unit, so as to provide an adequate gate-to-source bias to turn on a P-channel
16
of said PMOS single-transistor memory unit; biasing said P type doped drain region of said PMOS single-transistor memory unit to a bit line voltage V
BL
, wherein said bit line voltage V
BL
is smaller than said source line voltage V
SL
, so as to provide a lateral electric field for P-channel hot holes, wherein said lateral electric field forces said P-channel hot holes passing through said P-channel in an accelerated drifting rate to said P type doped drain region, thereby inducing hot electrons near said P type doped drain region, and wherein some of induced hot electrons inject into said ONO dielectric stack; and biasing said N-well to a well voltage V
NW
, wherein said well voltage V
NW
is equal to said source line voltage V
SL
.
In accordance with one preferred embodiment of this invention, the word line voltage V
WL
is between 0~4V, the source line voltage V
SL
is between 3~5V, the bit line voltage V
BL
is 0V, and the well voltage V
NW
is between 3~5V. In accordance with another preferred embodiment of this invention, the word line voltage V
WL
is between −1~−5V, the source line voltage V
SL
is 0V, the bit line voltage V
BL
is between −3~−5V, and the well voltage V
NW
is between 0V.
According to one aspect of the present invention, a method for programming a PMOS single-transistor memory unit based on band-to-band tunneling mechanism is disclosed. The PMOS single-transistor memory unit is comprised of a silicon dioxide-silicon nitride-silicon dioxide (ONO) dielectric stack disposed on an N-well, a P type polysilicon gate disposed on the ONO dielectric stack, a P type doped source region disposed in the N-well at one side of the P type polysilicon gate, and a P type doped drain region disposed in the N-well on the other side of the P type polysilicon gate. The method comprises: biasing said P type polysilicon gate of said PMOS single-transistor memory unit to a word line voltage V
WL
>0V; floating said P type doped source region of said PMOS single-transistor memory unit; and biasing said P type doped drain region of said PMOS s
Chou Jih-Wen
Chu Chih-Hsun
Hsu Ching-Hsiang
Huang Cheng-Tung
e-Memory Technology, Inc.
Hsu Winston
Phan Trong
LandOfFree
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