Semiconductor integrated circuits and fabricating method...

Details Semiconductor integrated circuits and fabricating method... Semiconductor integrated circuits and fabricating method...

2003-04-11

2004-02-17

Thompson, Craig A. (Department: 2813)

Electricity: electrical systems and devices

Electrostatic capacitors

Fixed capacitor

C257S068000

Reexamination Certificate

active

06693792

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention concerns semiconductor integrated circuits and a fabrication method thereof and, more in particular, it relates to a technique effective to be applied to semiconductor integrated circuits having DRAM (Dynamic Random Access Memory)
2. Description of the Prior Art
DRAM is constituted by arranging memory cells each comprising a selection transistor and information storage capacitor (hereinafter referred to as a capacitor) connected therewith in a matrix form on a semiconductor substrate. For constituting DRAM of an increased capacitance, densification of the static capacitance of the memory cell capacitor is necessary. As the technique therefor Japanese Patent Laid-open No.HEI 06-244364, for example, discloses a method of using tantalum pentaoxide having a high dielectric constant for the dielectric film of the capacitor. In this conventional technique, a silicon nitride film is formed on the surface of polycrystal silicon as an electrode by a thermal nitridation method using ammonia to prevent oxidation of the electrode upon heat treatment of the tantalum pentaoxide film in an oxygen atmosphere. Further, Japanese Patent Laid-open No.HEI 11-26712, for example, discloses a conventional technique of forming semi-spherical silicon oxide crystal on the surface of a polycrystal silicon electrode,forming silicon nitride film and tantalum pentaoxide in the same manner to constitute a capacitor. According to the conventional technique, static capacitance can be enlarged due to high dielectric constant of tantalum pentaoxide and increase in the effective electrode surface with the semi-spherical silicon crystal.
SUMMARY OF THE INVENTION
The present inventors have made a study on the capacitor for use in DRAM for the semiconductor integrated circuits of enlarged capacitance such as DRAM of 256 Mbits or 1 Gbit.
In the capacitor process, when thermal nitridation was conducted at 800° C. using ammonia, oxidation of the silicon nitride film occurs during the heat treatment for crystallization of tantalum pentaoxide (800° C. in oxygen), to lower the capacitance of the capacitor. Generally, as the reference of the capacitance density of a capacitor, a film thickness equivalent to a silicon oxide film having a relative of 3.9 dielectric constant is used. Reduction of the equivalent thickness means increase in the capacitance density of the capacitor.
In the case mentioned above, the equivalent thickness of the capacitor after the crystallization treatment was 3.3 nm (effective equivalent thickness of capacitor is 1.65 nm since the effective electrode surface area can be doubled by the semi-spherical silicon crystal). Then, the application limit of the capacitor has been studied. For preventing soft errors and preventing reading errors, the capacitance of a capacitor to be stored in the capacitor per 1 bit should be at least 25 fF or more.
FIG. 9
shows a relation between the feature size of capacitors and the aspect ratio of a storage node for attaining 25 fF of capacitor capacitance per 1 bit (ratio between the storage node height and the feature size). It was compared for the equivalent thickness of the capacitor of 1.5 nm, 2.0 nm, 2.5 nm and 3.0 nm, and conventional 3.3 nm, respectively. The fabrication limit for preparing a rugged storage node by the application of the semi-spherical silicon crystal was at an aspect ratio of 15 in view of the yield. That is, when the feature size is 0.13 &mgr;m, the height of the storage node is 2.0 &mgr;m. It can be seen from
FIG. 9
that the capacitor having 3.3 nm of equivalent thickness has an application limit in DRAM having a feature size of 0.16 &mgr;m. For attaining DRAM of higher speed and enlarged capacitance, the fabrication feature should be further reduced to 0.15 &mgr;m or less. For this purpose, the equivalent thickness of capacitor has to be reduced at least to 3.0 nm or less as can be seen from FIG.
9
.
The present inventors have further analyzed the capacitor in details. The temperature necessary for the crystallization of tantalum pentaoxide is at least 700° C. By the crystallization, tantalum pentaoxide crystallizes from an amorphous structure with a relative dielectric constant of 25 into a &dgr;-phase structure the relative dielectric constant increased to 40-60. However, since crystallization and oxidation of the silicon nitride film occur concurrently, the effect of increasing the dielectric constant was offset by the lowering of the capacitance due to oxidation of the silicon nitride film. When the temperature of heat treatment for crystallization was lowered to 700° C., oxidation of the silicon nitride film could be suppressed somewhat and the equivalent thickness could be reduced to 3.1 nm, but this resulted in a problem of increasing the leakage current density. When the leakage current of the capacitor is large, since the time till the loss of once stored information is shortened, the refresh time up to writing of the information once more is shortened to hinder high speed operation. As a threshold value, the leakage current should be 1 fA or less when a voltage of 1 V is added per 1 bit.
This invention intends to provide a capacitor having a capacitance density of a capacitor with a thickness equivalent to a silicon oxide film being 3.0 nm or less and with a leakage current of 1 fA or less upon application of a positive bias of 1 V per 1 bit on a rugged polycrystal silicon electrode, required for the fine semiconductor integrated circuits as described above.
The semiconductor integrated circuit according to this invention has a capacitor comprising a lower electrode having a polycrystal silicon film and semi-spherical silicon crystals formed on the surface thereof, a first dielectric film of 2.5 nm or more of physical thickness in contact with the lower electrode and a second dielectric film made of tantalum pentaoxide. The first dielectric film is a film of 2.5 nm or more capable of suppressing tunneling of electron from the inside of the polycrystal silicon film into tantalum pentaoxide. The film can include, for example, Al
2
O
3
, a mixed phase of Al
2
O
3
and SiO
2
, ZrSiO
4
. HfSiO
4
, a mixed phase of Y
2
O
3
and SiO
2
, a mixed phase of La
2
O
3
and SiO
2
and a silicon nitride film.
The effect of capacitors formed by applying the interface films as a feature of this invention is to be explained with reference to FIG.
1
.
FIG. 1A
shows a relation of film thickness for the thickness of the interface film and the thickness of the tantalum pentaoxide after completion of capacitors where the leakage current of capacitors is 1 fA or less when the positive bias of 1 V is applied to the plate electrode. All of the capacitors are applied with thermal treatment for crystallization in oxygen at 750° C. for 5 min. It can be seen from
FIG. 1A
that the thickness of tantalum pentaoxide required to suppress the leakage current to 1 fA or less (when the positive bias of 1 V is applied to the plate electrode) increases abruptly as the interface thickness is decreased. Further, it can also be seen that the trend does not depend on the interfacial film. For making the equivalent thickness of capacitor thin, it is simply considered that reduction of the thickness of the interfacial film of low dielectric constant is important. However, the result of, FIG.
1
(
a
) shows that a substantial lower limit exists for the interfacial film thickness in order to suppress the leakage current.
FIG. 1B
shows a relation between the equivalent thickness and the interfacial thickness of capacitors having the thickness for the interfacial film and the tantalum pentaoxide shown in FIG.
1
A. The abscissa indicates the thickness of the interfacial film after completion of the capacitor. The ordinate indicates a result of measurement for the equivalent thickness of capacitor having the thickness of the tantalum pentaoxide given by FIG.
1
A. It can be seen that along with increase in the interfacial thickness, the equivalent thickness once shows a minimum value and then turns to i

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