Clock pulse generating circuits

Details Clock pulse generating circuits Clock pulse generating circuits

1989-06-29

1991-04-02

Heyman, John S.

Electrical pulse counters, pulse dividers, or shift registers: c

Systems

Using particular code or particular counting sequence

377107, 377 75, 377 78, 307269, 307470, 307593, 307597, 328119, 328 72, H03K 519, H03K 2112

Patent

active

050051938

ABSTRACT:
A clock generating circuit for use in a signal processing circuit to enable it to be synchronized with other circuits in response to a reset signal uses a multi-state circuit which is cyclically stepped through its states by a clock drive signal and a decoder responsive to the state of the multi-state circuit to produce the required clock pulses. The reset signal is used to stop the multi-state circuit at a particular state and hold it there for a period of time enabling other similar clock pulse generating circuits to reach the same state and be held there. At the end of the period of time the multi-state circuits resume their cyclic stepping with all the circuits in synchronism.

REFERENCES:
patent: 3391305 (1968-07-01), Bradwin et al.
patent: 3673390 (1972-06-01), Krebs
patent: 4438357 (1984-03-01), Wicnienski
patent: 4528629 (1985-07-01), Breitling
patent: 4768210 (1988-08-01), Pockrandt
patent: 4797585 (1989-01-01), Segawa

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