Flash EEPROM memory with improved discharged speed using substra

Details Flash EEPROM memory with improved discharged speed using substra Flash EEPROM memory with improved discharged speed using substra

1995-06-05

1998-01-13

Louis-Jacques, Jacques

Boots, shoes, and leggings

36518527, 36518518, 3651853, 36518523, 257321, 257322, 437 33, 437 35, G06F 1500, G11C 1140

Patent

active

057085889

ABSTRACT:
A floating gate cell memory device, such as an EPROM or flash EEPROM, with improved discharge speed. A negative bias is applied to the effective substrate during discharge. The negative bias increases the electric field near the junction, thereby increasing the number of hot holes which can be injected to the floating gate, improving discharge speed.

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