Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Of specified material other than unalloyed aluminum
Reexamination Certificate
2002-01-24
2004-12-07
Nelms, David (Department: 2818)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Of specified material other than unalloyed aluminum
C257S690000, C257S698000, C257S748000
Reexamination Certificate
active
06828681
ABSTRACT:
Applicant hereby incorporates by reference Japanese Application No. 2001-015671, filed Jan. 24, 2001, in its entirety.
TECHNICAL FIELD
The present invention includes semiconductor devices having a bonding pad region and methods for manufacturing the same.
RELATED ART
Presently, with further miniaturization of semiconductor devices being advanced, wiring layers in semiconductor devices are formed in multiple layers. A semiconductor device is generally provided with a pad opening section that reaches the uppermost layer among the wiring layers. The exterior and the uppermost layer among the wiring layers are electrically connected through the pad opening section.
FIG. 9
schematically shows a cross-sectional view of a pad forming region of a semiconductor device. Generally, wiring layers
332
and
330
that are formed at a level below the wiring layer
340
which the pad opening section reaches are also formed in a region below the pad opening section
360
. However, when the wiring layers
332
and
330
are formed in a region below the pad opening section
360
, cracks
310
may be generated in interlayer insulation layers
322
and
324
, when wiring bonding is carried out at the pad opening section
360
.
SUMMARY
Certain embodiments relate to a semiconductor device including a protective insulation layer, a pad opening section provided in the protective insulation layer, a wiring layer which the pad opening section reaches, and a wiring layer provided at a level lower than the upper wiring layer. The wiring layer provided at a level lower than the wiring layer which the pad opening section reaches is formed outside a region of the pad opening section as viewed in a plan view.
Embodiments also relate to a semiconductor device including a first wiring layer formed above a semiconductor layer through a first interlayer insulation layer, a second wiring layer that provides a pad section formed above the first wiring layer through a second interlayer insulation layer, a protective insulation layer formed above the second wiring layer and the second interlayer insulation layer, and a pad opening section provided in the protective insulation layer. An upper surface of the first interlayer insulation layer includes a first region where the protective insulation layer is formed vertically thereabove, and the first wiring layer is formed on the first region.
Embodiments also relate to a method for manufacturing a semiconductor device, the method including the steps of: (a) forming a wiring layer on an interlayer insulation layer; (b) forming a protective insulation layer on the interlayer insulation layer and the wiring layer; and (c) forming a pad opening section in the protective insulation layer, which reaches the wiring layer. The semiconductor device is formed to include a wiring layer provided at a level lower than the wiring layer to which the pad opening section reaches. The pad opening section is formed such that the wiring layer provided at a level lower than the wiring layer to which the pad opening section reaches is formed outside a region of the pad opening section as viewed in a plan view.
Embodiments also relate to a method for manufacturing a semiconductor device, including forming a lower level wiring layer; forming an lower level interlayer dielectric layer on and adjacent to the lower level wiring layer; forming an upper level wiring layer above the lower level interlayer dielectric layer, wherein the lower level wiring layer is electrically connected to the upper level wiring layer; and forming a protective insulation layer on the upper level wiring layer. The method also includes removing a first portion of the protective insulation layer over the upper level wiring layer and over the lower level interlayer dielectric layer to form a pad opening section in the upper level wiring layer, wherein a second portion of the protective insulation layer located vertically above the lower level wiring layer remains after removing the first portion of the protective layer; and wherein no portion of the lower level wiring layer is disposed vertically below the pad opening section.
REFERENCES:
patent: 4984061 (1991-01-01), Matsumoto
patent: 5149674 (1992-09-01), Freeman et al.
patent: 5700735 (1997-12-01), Shiue et al.
patent: 5736791 (1998-04-01), Fujiki et al.
patent: 5820926 (1998-10-01), Lien
patent: 5939790 (1999-08-01), Gregoire et al.
patent: 6197685 (2001-03-01), Domae et al.
patent: 6313537 (2001-11-01), Lee et al.
patent: 6362528 (2002-03-01), Anand
patent: 6476491 (2002-11-01), Harada et al.
patent: 64-081236 (1989-03-01), None
patent: 08-213422 (1996-08-01), None
patent: 11-145288 (1999-05-01), None
patent: 11-186320 (1999-07-01), None
Notice of Reasons of Rejection for Japanese Patent Application No. 2001-015671 (from which priority is claimed in U.S. Ser. No. 10/053,910), dated Mar. 25, 2003, which lists JP11-186320, JP08-213422, JP64-081236, and JP11-145288.
Ho Tu-Tu
Konrad Raynes & Victor LLP
Nelms David
Raynes Alan S.
Seiko Epson Corporation
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