Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Synchronizing
Reexamination Certificate
2003-10-03
2004-12-28
Nguyen, Linh My (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Synchronizing
C327S161000
Reexamination Certificate
active
06836163
ABSTRACT:
BACKGROUND OF THE INVENTION
The invention relates generally to semiconductor integrated circuit (IC) devices and more particularly, it relates to differential output structures with reduced skew for single inputs.
In the semiconductor IC industry, board manufacturers are challenged with integrating products with different input and output standards, e.g., TTL (Transistor Transistor Logic) to LVDS (Low Voltage Differential Swing), LVTTL (Low Voltage Transistor Transistor Logic) to LVDS, etc. Typically, when a single input standard such as LVTTL is converted to a differential output standard such as LVDS, the two differential outputs are skewed apart from one another by at least one gate delay, as will be illustrated with reference to FIG.
1
.
FIG. 1
shows a conventional differential output structure
10
, in which a single input A is used to generate two differential and complimentary output signals on output M and output N. In
FIG. 1
, there are three inverters
12
,
16
and
18
between input A and point D and two inverters
26
and
28
between input A and point F. The difference of one inverter or one gate delay between path
1
(from input A to point D) and path
2
(from input A to point F) will cause switching noise on output M and output N, which is related to the skew between node D and node F. Switching noise is caused when the same logic level appears on output M and output N. All outputs have some switching noise caused by skew. However, too much skew or switching noise can render a product unusable because it will cause improper logic or clock translation in a receiver which the differential output is driving.
Some solutions have been proposed to limit the skew. One solution is to change the ratios of width/length (W/L) of the inverters in path
1
and path
2
in order to match skews at point D and point F in FIG.
1
. Another solution is to make the sums of the channel lengths and widths of the inverters in path
1
equal to the sums of the channel lengths and widths in path
2
, respectively, as follows:
L
12
+L
16
+L
18
=L
26
+L
28
W
12
+W
16
+W
18
=W
26
+W
28
where L
12
, L
16
, L
18
, L
26
and L
28
are the channel lengths of inverters
12
,
16
,
18
,
26
and
28
, respectively; and W
12
, W
16
, W
18
, W
26
and W
28
are the channel widths of inverters
12
,
16
,
18
,
26
and
28
, respectively.
However, these proposed solutions suffer from several drawbacks. When an inverter chain is laid out, a good design practice is to characterize the process and determine the ratio of PMOS (p-type metal oxide semiconductor) and NMOS (n-type metal oxide semiconductor), which gives the desired power consumption, speed, duty cycle, propagation time, etc. For most processes, the ratio of PMOS width (Wp) to NMOS width (Wn) is typically between 2 and 3 to 1. By not using a constant Wp to Wn ratio in the proposed solutions described above, it makes matching every differential inverter path a numerical problem. Moreover, the non-ratioed changing of the length for the PMOS and NMOS devices compounds the problem even further since different lengths and widths add additional processing variations.
Therefore, there is a need for an improved differential output structure with reduced skew, while introducing less process variations.
SUMMARY OF THE INVENTION
The invention provides an improved differential output structure with minimal skew and introduces less process variations.
According to one embodiment of the invention, a differential output structure is provided and comprises an input line, an output driver and a sync circuit. The input line includes first and second paths. The first path has an input end for receiving input signals. The first path also has an output end and includes at least one driving element. The second path has an input end operably coupled to the input end of the first path for receiving the input signals. The second path also has an output end. The output driver is operably coupled to the output ends of the first and second paths and is configured to provide differential outputs. The sync circuit is operably coupled between the first and second paths and is configured to synchronize the speed of signals traveling on the two paths.
Other objects and attainments together with a fuller understanding of the invention will become apparent and appreciated by referring to the following description and claims taken in conjunction with the accompanying drawings.
REFERENCES:
patent: 5375148 (1994-12-01), Parker et al.
patent: 6107847 (2000-08-01), Johnson et al.
patent: 6420920 (2002-07-01), Huber et al.
Koninklijke Philips Electronics , N.V.
Nguyen Linh My
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