Excavating
Patent
1994-09-26
1996-04-16
Beausoliel, Jr., Robert W.
Excavating
371 225, 371 226, 39518306, 324765, 365201, G11C 2900
Patent
active
055090192
ABSTRACT:
A semiconductor integrated circuit includes a chip (10a), a core area (12) on the chip in which tester circuits (14) are placed, and an I/O area (13) on the chip. The I/O area is provided at the periphery of the core area, and in the I/O area a plurality of tester circuits (17) are placed for testing the functions of respectively testee circuits in, respectively core area. The I/O area is provided with test control circuits (15) for supplying a control signal (C2) and a clock signal (C3), for testing said tester circuits, to the test circuits and testee circuits, on the basis of an external control signal supplied from outside.
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Beausoliel, Jr. Robert W.
Fujitsu Limited
Le Dieu-Minh
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