Static information storage and retrieval – Floating gate – Particular connection
Reexamination Certificate
2002-11-21
2004-12-28
Elms, Richard (Department: 2824)
Static information storage and retrieval
Floating gate
Particular connection
C365S185120, C365S238500
Reexamination Certificate
active
06836434
ABSTRACT:
BACKGROUND OF THE INVENTION
I. Field of the Invention
The present invention relates generally to memory devices and particularly to flash memory devices.
II. Description of the Related Art
Flash memory devices have developed into a popular source of non-volatile memory for a wide range of electronic applications. Flash memory devices typically use a one-transistor memory cell that allows for high memory densities, high reliability, and low power consumption. Common uses for flash memory include portable computers, personal digital assistants (PDAs), digital cameras, and cellular telephones. Program code, system data such as a basic input/output system (BIOS), and other firmware can typically be stored in flash memory devices.
A synchronous flash memory device is a type of flash memory device that has a synchronous dynamic random access memory (SDRAM) interface for read operations. This enables the synchronous flash memory device to operate at much higher speeds than a typical flash memory by opening a page (i.e., a row) of 8000 bits at one time. This increases the synchronous flash device's performance at the expense of higher current usage.
FIG. 1
illustrates a simplified block diagram of a typical prior art synchronous flash memory array (
100
) architecture. The memory array (
100
) generally consists of a number of memory array banks (
102
,
104
,
106
,
108
) that have rows (
110
) and columns (
112
). A memory bank (
102
,
104
,
106
,
108
), upon being accessed with a bank, row, and column address, loads an internal data latch circuit (
114
) with a defined number of bits.
When a bank and row are selected by an input row address, the contents of the row of memory cells are placed on column bit lines coupled to sense amplifiers that are located in the latch circuitry block (
114
). The values detected by the sense amplifiers are latched into the latch circuitry (
114
). An input column address, that defines the column page, selects from the latches of the latch circuitry (
114
) and, thus, from the columns of the active row page.
To encompass a large variety of applications, chip designers make some restrictive choices in the characteristics of memory designs. These characteristics include current consumption and performance. The designers typically have to trade off one for the other since the faster the memory device, the higher the current consumption. For example, an electronic circuit that requires the speed of the synchronous flash has to live with relatively high current consumption as well. Whereas an electronic circuit that has the low current consumption of the virtual synchronous flash may sacrifice its performance somewhat.
Battery powered devices would benefit more from low power consumption than higher performance. Line powered devices would benefit more from faster performance than low power consumption. In order to satisfy both markets, flash memory designers typically have to design multiple versions of a memory. This requires more time and money on the part of the manufacturer. There is a resulting need in the art for a way to choose power consumption versus throughput in a single flash memory device.
SUMMARY
The present invention encompasses a flash memory device having a flash memory array that comprises a plurality of flash memory cells. A mode control register accepts a control word that selects between a page read mode and a portion/segment of page read mode.
In one embodiment, the flash memory device is coupled to a processor that generates the control word. The processor, in this embodiment, also generates the extended address lines required to access the segmented sections of the memory array when the flash memory device is in the segment read mode.
REFERENCES:
patent: 5570320 (1996-10-01), Runas
patent: 5787038 (1998-07-01), Park
patent: 5835414 (1998-11-01), Hung
patent: 6118705 (2000-09-01), Gupta et al.
patent: 6128675 (2000-10-01), Ko
patent: 6222767 (2001-04-01), Kendall et al.
patent: 6259645 (2001-07-01), Chen et al.
patent: 6381670 (2002-04-01), Lee et al.
patent: 6691219 (2004-02-01), Ma et al.
Elms Richard
Leffert Jay & Polglaze PA
Micro)n Technology, Inc.
Nguyen Dang T
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