Miscellaneous active electrical nonlinear devices – circuits – and – Specific identifiable device – circuit – or system – Nonlinear amplifying circuit
Reexamination Certificate
2002-12-19
2004-06-15
Le, Dinh T. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Specific identifiable device, circuit, or system
Nonlinear amplifying circuit
C330S252000
Reexamination Certificate
active
06750702
ABSTRACT:
TECHNICAL FIELD
The present invention relates to the field of limiting amplifiers.
BACKGROUND OF THE INVENTION
In wireless communication systems, such as cellular telephones, one of the significant problems is the fading phenomenon which causes fluctuations in the received signal's amplitude and phase which results in having a signal that has a wide dynamic range. At the receiving side, the received signal is handled by a receiver block that generally includes a gain amplifying chain which is adjusted to saturate the received signal at a relatively constant amplitude. To achieve this, the amplitude of the analog received signal is evaluated and converted into a digital word through an analog to digital (A/D) converter, and next the digital word feeds a Digital Signal Processor (DSP) to control back the gain of the amplifier circuit.
A direct A/D conversion may require the use of a large number of bits to represent the variation. As an example for an amplitude that varies from 500 &mgr;V to 500 mV, if a common A/D converter is used (i.e., a circuit having a LSB<500 &mgr;V), the number N of bits is at least N=10.
A known solution to reduce N is to compress the received signal by employing a logarithmic amplifier in a successive approximation. U.S. Pat. No. 3,745,374 describes a basic implementation of such facility. In Huang, et al., “A 2-V 10.7-MHz CMOS Limiting Amplifier/RSSI,” in the IEEE JOURNAL OF SOLID-STATE CIRCUITS, Vol. 35 No. 10, October, 2000, a logarithmic architecture is described in FIG.
2
. The circuit is composed of a limiting amplifier in a cascade structure in combination with several full-wave rectifiers.
The drawbacks of the existing solutions are on one hand that these circuits are sensitive to process variations and on the other hand they are still having a too high current consumption.
Thus, there is a need for an easy to implement limiting amplifier having a low power consumption. Moreover, there is a need for a limiting amplifier having a gain and an input voltage saturation that are independent over the process and the temperature variations.
The present invention is directed towards solving those problems.
SUMMARY OF THE INVENTION
It is thus an object of the present invention to provide a reliable and accurate system that is independent over process and temperature variations.
Another object of the invention is to provide a small area system suitable for implementation into nowadays integrated circuits.
Still another object of the invention is to decrease the power consumption.
In view of the foregoing and other problems of the conventional systems and methods, these objects are achieved by a system as described in the appended claims.
In a preferred embodiment, the limiting amplifier comprises a differential amplifying stage combined with a differential output stage. The differential amplifying stage comprises first and second input transistors having:
first and second input terminals coupled to a differential input voltage,
first and second high terminals respectively coupled to a high power supply through first and second load means, and
first and second low terminals respectively coupled to a low power supply through first and second current source means.
The differential output stage comprises third and fourth input transistors having:
third and fourth input terminals respectively connected to the first and second high terminals,
differential output terminals respectively connected to third and fourth current source means, and
high terminals connected to the high power supply.
The system is characterized in that a first resistor means is connected between the first and the second low terminals of the differential amplifying stage, and a second resistor means is connected between the differential output terminals of the differential output stage, thereby providing a gain equal to the ratio of the two resistor means.
In an improved embodiment, a first and a second operational amplifier means are coupled to the input of the differential amplifying stage.
In application, the system is preferably used in conjunction with a full wave rectifier arrangement coupled to the first and the second high terminals of the differential amplifying stage.
To achieve a logarithm function, a plurality of series connected limiting amplifiers and full wave rectifiers are chained for providing an output signal representative of the logarithm of an input signal.
REFERENCES:
patent: 3745374 (1973-07-01), Hecker et al.
patent: 4198602 (1980-04-01), Nishijima et al.
patent: 4571502 (1986-02-01), Kimura et al.
patent: 5349521 (1994-09-01), Menegoli et al.
patent: 5570055 (1996-10-01), Gilbert
patent: 6229375 (2001-05-01), Koen
Huang, et al., “A 2-V 10.7-MHz CMOS Limiting Amplifier/RSSI,” in the IEEE Journal of Solid-State Circuits, vol. 35, No. 10, Oct., 2000.
Le Dinh T.
Pepper Margaret A.
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