Active solid-state devices (e.g. – transistors – solid-state diode – Regenerative type switching device
Reexamination Certificate
2003-04-25
2004-08-31
Cao, Phat X. (Department: 2814)
Active solid-state devices (e.g., transistors, solid-state diode
Regenerative type switching device
C257S341000, C257S401000
Reexamination Certificate
active
06784465
ABSTRACT:
BACKGROUND OF THE INVENTION
This application is a division of application Ser. No. 09/747,757, filed Dec. 22, 2000, now U.S. Pat. No. 6,579,782 entitled “Vertical Power Component Manufacturing Method,” which prior application is incorporated herein by reference.
1. Field of the Invention
The present invention relates to vertical type power components capable of withstanding high voltages.
2. Discussion of the Related Art
FIG. 1
is a very simplified cross-section view illustrating the general construction of a conventional power component. This component is formed in a large silicon wafer and is surrounded at its external periphery with an isolating wall of a conductivity type opposite to that of the substrate. This isolating wall is intended to separate the component from other components of the same chip, or for creating an electrically inactive protection area at the border of a chip, where a cutting is performed with respect to a neighboring chip. More specifically, referring to
FIG. 1
, starting from an N-type substrate
1
, a first manufacturing operation consists of forming, from the upper and lower surfaces of this substrate, drive-in regions
2
and
3
that join to form the isolating wall.
For practical reasons, the wafers cannot have thicknesses under 200 &mgr;m. Under this threshold, they would be likely to break easily in handling associated with manufacturing. Thus, each of drive-ins
2
and
3
must penetrate into the wafer by some hundred um, for example, 125 &mgr;m for a wafer of a thickness from 210 to 240 &mgr;m, to ascertain that a continuous wall, sufficiently doped at the level of its median portion, is formed. This implies very long diffusions at high temperatures, for example 300 hours at 1280° C. Clearly, this operation must be performed on a silicon wafer before any other doping operation on this wafer. Otherwise, during this long thermal processing time, the implantations previously performed in the substrate would diffuse too deeply.
After forming the isolating walls, doped regions intended for forming the desired vertical component, for example, as shown in
FIG. 1
, a thyristor, are formed. For this purpose, a P-type region
4
corresponding to the thyristor anode may be formed on the entire lower substrate surface, simultaneously with a P-type region
5
corresponding to the cathode gate region of this thyristor, on a portion of the upper substrate surface. Then, on the upper surface side, an N+ diffusion is performed to form in region
5
a cathode region
6
and possibly, between region
5
and isolating wall
2
, a peripheral channel stop ring
7
.
As seen previously, the total thickness of the wafer is determined by manufacturing considerations, which are essentially mechanical. Further, the characteristics of P-type regions
4
and
5
are determined by the desired electric characteristics of the thyristor. Indeed, it is for example desired to have a sufficiently steep doping front between each of regions
4
and
5
and substrate
1
to improve the characteristics of the corresponding junctions, and especially to obtain a good injection characteristic of the PNP transistor at the level of the junction between substrate
1
and region
4
, but not too steep to obtain a sufficiently fast component.
Thus, in the case of the shown thyristor, if each of diffusions
4
and
5
has a depth on the order of 40 &mgr;m, and if the wafer has a 210-&mgr;m thickness, there will remain between P-N junctions
5
-
1
and
4
-
1
an area of substrate
1
having a 130-&mgr;m thickness. As is well known, this area of the substrate provides its off-state breakdown voltage characteristics to the power device. This area must thus be sufficiently thick. However, an excessive thickness of this area results in an increase of on-state losses of the power device. If a power device having a breakdown voltage on the order of 400 volts is desired to be obtained, it would be sufficient for the thickness of the region of substrate
1
to be on the order of 40 &mgr;m whereas, with the described manufacturing method, a thickness on the order of 130 &mgr;m is inevitably provided. No simple way of solving this problem is currently known. Indeed, increasing, for example, the thickness of layer
4
has the consequence that the junction profile of this layer risks not fulfilling the desired electric conditions. For example, if a thyristor such as shown in
FIG. 2
is formed, in which the rear surface P region results from drive-in
3
that is used to form the lower isolating wall, a very progressive junction will be obtained and the thyristor characteristics will be rather unsatisfactory. Indeed, the substrate thickness that is involved to determine the on-state resistance no longer essentially is the thickness of N region
1
, but also is a portion of the thickness of P region
3
. Further, the breakdown voltage decreases.
More generally, the same problem is raised with any power device to be surrounded with an isolating wall, having a rear surface of a doping type opposite to that of a breakdown voltage substrate, for example a power transistor or an IGBT transistor.
A first solution to solve this problem has been described in a patent application, filed on Dec. 14, 2000, which is incorporated herein by reference and which describes a structure such as shown in FIG.
3
.
On a relatively heavily-doped P-type substrate
10
is formed, by epitaxy, a lightly-doped N-type layer
11
intended for forming the breakdown voltage layer of a vertical power component, of which the P substrate forms the lower surface anode. An isolating wall is formed by forming a trench
13
substantially crossing the thickness of epitaxial layer
11
and surrounding the component, then filling the trench with heavily-doped P-type polysilicon and performing a thermal diffusion step.
The trench may be formed of openings sufficiently close to one another for diffused areas
14
laterally extending from these openings to join and form the isolating wall. The openings may, for example, have a diameter on the order of 1 to 5 &mgr;m and be distant from one another by 2 to 10 &mgr;m.
Then, diffusions intended for forming a desired component, for example a cathode gate diffusion
5
and cathode and channel stop ring diffusions
6
and
7
will be conventionally formed. Preferably, to improve the quality of the isolating wall, at the same time as P-type diffusion
5
is formed, a diffusion may be performed into areas
16
corresponding to the high portion of the isolating wall, to increase the doping level at the upper surface of the isolating wall.
A second isolating wall
17
may be formed outside the first one. A cutting may be performed between the two isolating walls distant, for example, by 100 &mgr;m, to separate two chips of a wafer.
The solution hereabove is not always satisfactory, since the doping gradient at the junction between substrate
10
and epitaxial layer
11
cannot be controlled. Further, this solution is not adapted to the more and more frequent case in which specific diffused areas are desired to be formed on the rear surface side.
SUMMARY OF THE INVENTION
Thus, an object of the present invention is to provide a novel method of manufacturing power components that improves or optimizes the thickness of the most lightly-doped breakdown voltage layer, avoiding the very long diffusion steps, and improving or optimizing the doping between anode and substrate.
The present invention also aims at a component obtained by the described method.
To achieve these and other objects, the present invention provides a method for manufacturing a vertical power component on a substrate formed of a lightly-doped silicon wafer, including the steps of boring on the lower surface side of the substrate a succession of holes perpendicular to this surface; diffusing a dopant from the holes into the substrate, of a second conductivity type opposite to that of the substrate; and boring similar holes on the upper surface side of the substrate to define an isolating wall and diffusing from these holes into the sub
Cao Phat X.
Doan Theresa T.
Jorgenson Lisa K.
Morris James H.
STMicroelectronics S.A.
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