Method to predict dielectric film properties using chemical...

Details Method to predict dielectric film properties using chemical... Method to predict dielectric film properties using chemical...

2000-07-24

2004-12-28

Picard, Leo (Department: 2125)

Data processing: generic control systems or specific application

Specific application, apparatus or process

Product assembly or manufacturing

C700S029000, C700S108000, C703S013000, C703S014000

Reexamination Certificate

active

06836693

ABSTRACT:

BACKGROUND OF THE INVENTION
(1) Field of the Invention
The invention relates to the fabrication of integrated circuit devices, and more particularly, to a method for determining dielectric film properties. The method of the invention uses computer modeling of dielectric film properties whereby chemical bonding measurements are the input data that are provided to the computer model.
(2) Description of the Prior Art
Dielectric materials are arguably one of the most frequently applied materials in the creation of semiconductor devices. A wide range of materials can be used as a dielectric material, such materials can for instance contain silicon dioxide (“oxide”, doped or undoped) or silicon nitride (“nitride”), silicon oxynitride, fluoropolymer, parylene, polyimide, tetra-ethyl-ortho-silicate (TEOS) based oxides, boro-phosphate-silicate-glass (BPSG), phospho-silicate-glass (PSG), boro-silicate-glass (BSG), Pxide-nitride-oxide (ONO), a low dielectric constant material, such as hydrogen silsesquioxane and HDP-FSG (high-density-plasma fluorine-doped silicate glass. The most commonly used and therefore the preferred dielectrics are silicon dioxide (doped or undoped), silicon oxynitride, parylene or polyimide, spin-on-class, plasma oxide or LPCVD oxide. The preferred dielectric material to be used for the invention is SiO
2
. Typical conditions for the deposition of a layer of dielectric uses, for instance, PECVD procedures at a temperature of between about 350 and 450 degrees C. to a thickness between about 5000 and 10,000 Angstrom using TEOS as a source. The preferred etching conditions for the TEOS etch are using CF
4
or CHF
3
as the etchant gas at a flow rate of about 15 sccm, gas pressure about 800 mTorr, rf power density about 400 Watts, with no magnetic field applied, ambient wafer temperature with a time of the etch of about 10 seconds. One of the more interesting dielectric materials that has received increased attention and application is conventional polyimides, which have a number of attractive characteristics for their application in a semiconductor device structure such as the ability to fill openings of high aspect ratio, a relatively low dielectric constant (about 3.2), a simple process required for the depositing of a layer of polyimide, the reduction of sharp features or steps in the underlying layer, high temperature tolerance of cured polyimide. Photosensitive polyimides have these same characteristics but can, in addition, be patterned like a photoresist mask and can, after patterning and etching, remain on the surface on which it has been deposited to serve as a passivation layer. The process of depositing and patterning polyimide is relatively simple and is well understood in the art. Polyimide is typically spun on in the form of a liquid (polyamic-acid precursor). After spin-on, the polyimide may be cured whereby the spun-on polyimide becomes a solid polyimide film. Etching of the cured film often uses oxygen or fluorine based plasma. Polyimide is typically applied over the entire substrate followed by a baking step to cure and evaporate the solvents in the polyimide. Curing of the polyimide provides extra protection to the device circuitry. This step is typically a high temperature cure, at 350 to 400 degrees C., in a N
2
gas ambient for a time period between about 1.5 and 2.5 hours. Polyimide provides extra protection to the surface of the silicon chip against scratching, cracking and other types of mechanical damage. Most often, mechanical damage occurs during assembly, packaging or any subsequent handling of the die. As a passivation layer, polyimide also guards against thin film cracking which frequently results from the packaging of very large dies into plastic packages. A passivation layer can contain silicon oxide/silicon nitride (SiO
2
/Si
3
N
4
) deposited by CVD, a passivation layer can however also be a photosensitive polyimide or can comprise titanium nitride. Another material often used for passivation layer is phosphorous doped silicon dioxide that is typically deposited over a final layer of aluminum interconnect using a Low Temperature CVD process.
Dielectric materials find numerous applications in the formation of semiconductor devices. For instance, spacers that are formed on the sidewalls of gate electrodes can be made using silicon-nitride or silicon-oxide, BSG, PSG, polysilicon, other materials preferably of a dielectric nature, CVD oxide formed from a TEOS source. Often used are amorphous materials that inhibit the deposition of epitaxial silicon thereupon. A silicon oxide spacer can be formed via anisotropic RIE of said silicon oxide layer, using CHF
3
or CF
4
—O
2
—He as an etchant. A silicon nitride spacer can be formed via anisotropic RIE of said silicon nitride layer, using CHF
3
or SF
6
—O
2
as an etchant.
Dielectric materials are frequently used for the creation of conductive interconnect lines, via or contact openings. In the formation of semiconductor integrated circuits, it is common practice to form interconnect metal line structures on a number of different levels within the structure and interconnecting the various levels of wiring with contact or via openings.
The first or lowest level of interconnect wires is typically formed in a layer of dielectric as a first step in the process after which a second or overlying level of interconnect wires is created in an overlying layer of dielectric over the first level.
The first level of interconnect wires is typically in contact with active regions in a semiconductor substrate but is not limited to such contact. The first level of interconnect can for instance also be in contact with a conductor that leads to other devices that form part of a larger, multi-chip structure.
The two levels of metal wires are connected by openings between the two levels, these openings are created in layers of surrounding dielectric and are filled with metal where the openings align with contact points in one or both of the levels of metal lines.
Previously used techniques to form multi-levels of wiring apply the technique of first forming the interconnect level metal in a first plane followed by forming the overlying level of interconnect wire in a second plane. This structure typically starts with the surface of a semiconductor substrate into which active devices have been created. The surface into which the pattern of interconnect lines of the first plane is formed may also be an insulation layer deposited over the surface of the substrate or a layer of oxide may first have been formed on the surface of the substrate. After the layer, into which the pattern of interconnecting wires has to be created, has been defined, the interconnecting pattern itself needs to be defined. This is done using conventional photolithographic techniques whereby the openings are made (in the layer) above the points that need to be contacted in the substrate. The openings, once created, may by lined with layers of material to enhance metal adhesion (to the sidewalls of the opening), the glue layer, or to prevent diffusion of materials into and from the substrate in subsequent processing steps, the barrier layer. For the barrier layer, a variety of materials can be used such as Ti/Tin:W (titanium/titanium nitride:tungsten), titanium-tungsten/titanium or titanium-tungsten nitride/titanium or titanium nitride or titamium nitride/titanium, silicon nitride (Si
3
N
4
), tungsten, tantalum, niobium, molybdenum. The final phase in creating the first level of interconnect lines is to fill the created openings with metal, typically aluminum, tungsten or copper, dependent on the particular application and requirements and restrictions imposed by such parameters as line width, aspect ratio of the opening, required planarity of the surface of the deposited metal and others.
This process of line formation in overlying layers of metal can be repeated in essentially the same manner as highlighted above for the first layer of interconnecting wires.
This process of forming sequential layers of interconnecting levels of wire is in ma

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