Active solid-state devices (e.g. – transistors – solid-state diode – Integrated circuit structure with electrically isolated... – Including dielectric isolation means
Reexamination Certificate
2000-06-20
2004-02-24
Thomas, Tom (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Integrated circuit structure with electrically isolated...
Including dielectric isolation means
C257S510000, C257S514000, C257S515000, C257S619000, C257S623000
Reexamination Certificate
active
06696743
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor transistor and a process of manufacturing the same. More particularly, it relates to a trench-isolated semiconductor transistor and a process of manufacturing the same.
2. Description of Related Art
A semiconductor device as shown in FIGS.
10
(
a
) and
10
(
b
) has been proposed. In the semiconductor device, trench device isolation regions
31
are formed in a semiconductor substrate
30
and a MOS field effect transistor is formed between the trench device isolation regions
31
.
Typically, in such a transistor, a gate electrode
32
is formed on a device formation region
33
defined by the trench device isolation regions
31
and extends over the trench device isolation regions
31
(
2
C and
2
D in FIGS.
10
(
a
) and
10
(
b
)).
The surface of the trench device isolation region
31
may be positioned lower as shown in FIG.
10
(
a
) or higher as shown in FIG.
10
(
b
) than the surface of the device formation region
33
in accordance with variation in thickness of an insulating film occurring at the formation and etching of the insulating film, for example.
Where the surface of the trench device isolation region
31
is lower than the surface of the device formation region
33
as shown in FIG.
10
(
a
), a gate insulating film
34
is formed on the sides of the device formation region
33
(
2
A in FIG.
10
(
a
)) and a gate electrode
32
is formed thereon. In such a region, the gate insulating film
34
becomes thin because of changes in crystal orientation, stress during oxidization and the like. The thin gate insulating film
34
is liable to be stressed due to an electric field intensified in the operation of device, and thus the gate insulating film
34
may become less reliable.
Also in the case where the surface of the trench device isolation region
31
is higher than the surface of the device formation region
33
as shown in FIG.
10
(
b
), the width of the resulting gate electrode
32
varies because of the mal-alignment of both surfaces, which may seriously deteriorate transistor characteristics.
As shown in
FIG. 11
, Japanese Unexamined Patent Publication No. HEI 7(1995)-14916 proposes a semiconductor structure in which a gate electrode
42
is formed with a predetermined distance from trench device isolation regions
41
formed in a semiconductor substrate
40
, and an insulating film
44
is provided between the gate electrode
42
and the trench device isolation region
41
.
In this semiconductor device, a gate electrode wiring
43
is connected on the gate electrode
42
. Therefore, as the gate electrode
42
becomes thin according to the miniaturization of the semiconductor structure, a region (E in
FIG. 11
(
a
)) between the gate electrode
42
and the trench device isolation region
41
is reversed under the influence of an electric field of the gate electrode wiring
43
. This might induce erroneous operation of the transistor.
In order to prevent the reversal, a channel stopper is formed by introducing impurities between the gate electrode
42
and the trench device isolation region
41
. In this method, the impurities for the channel stopper enters below the gate electrode
42
and the threshold voltage increases in a region where the channel width of the transistor could be small, that is, a so-called narrow channel effect occurs.
Further, as shown in FIG.
12
(
a
), Japanese Unexamined Patent Publication No. HEI 9(1997)-283613 describes planarization of a semiconductor structure, in which i) a gate insulating film
51
, a first gate electrode
52
and a second gate electrode
53
are formed in this order on a semiconductor substrate
50
, ii) the second gate electrode
53
, the first gate electrode
52
, the gate insulating film
51
and the semiconductor substrate
50
are sequentially etched using the same mask pattern to form a trench
55
in the semiconductor substrate
50
, iii) an insulating film
54
is buried in the trench
55
and iv) the surface of the device is flattened by CMP method.
In this method, however, the semiconductor substrate
50
in which the trench
55
is formed may be damaged, and thereby a leak current might occur.
To solve this drawback, typically, an oxide film
56
is formed on the walls of the trench
55
after the trench
55
is formed in the semiconductor substrate
50
.
However, when the walls of the trench
55
thus constructed is oxidized, not only the walls of the trench
55
but also the sides of the gate insulating film
51
formed therealong are oxidized as shown in FIG.
12
(
b
), which forms a region called a gate bird's beak (N in FIG.
12
(
b
)). This causes the narrow channel effect.
SUMMARY OF THE INVENTION
The present invention is achieved in view of these drawbacks of the prior art and intended to provide a semiconductor transistor and a process of manufacturing the same, which lead to accurate formation of the gate electrode and good reliability of the gate insulating film and prevent leak current in the transistor due to a decrease in the threshold voltage as well as the narrow channel effect.
The present invention provides a semiconductor transistor formed between trench device isolation regions comprising;
a gate insulating film formed on a semiconductor substrate,
a gate electrode formed on a device formation region of the semiconductor substrate with the intervention of the gate insulating film and extended over the trench device isolation regions, a distance from an interface between the gate electrode and the gate insulating film to the surface of the device formation region and a distance from said interface to the trench device isolation region being the same, and
a gate electrode wiring formed in self-alignment with the gate electrode to have the same length as the length of the gate electrode and connected on the gate electrode on the device formation region.
Further, the present invention provides a process of manufacturing a semiconductor transistor comprising the steps of:
(i) forming a gate insulating film, a first conductive film, a first oxide film and a resist pattern for forming a trench device isolation region on a semiconductor substrate;
(ii) etching the first oxide film, the first conductive film and the gate insulating film using the resist pattern as a mask;
(iii) forming an oxidization protective film on the sides of the first oxide film, the first conductive film and the gate insulating film;
(iv) forming a trench in the semiconductor substrate using the first oxide film and the oxidization protective film as a mask, oxidizing the inside walls of the trench to form a second oxide film and removing the oxidization protective film;
(v) forming an insulating film on the entire surface of the semiconductor substrate including the trench;
(vi) removing the insulating film and the second oxide film until the first conductive film is exposed;
(vii) forming a second conductive film and a resist pattern for a gate electrode/a gate electrode wiring on the first conductive film; and
(viii) patterning the first and second conductive films using the resist pattern as a mask to form a gate electrode and a gate electrode wiring in self-alignment.
These and other objects of the present application will become more readily apparent from the detailed description given hereinafter. However, it should be understood that the detailed description and specific examples, while indicating preferred embodiments of the invention, are given by way of illustration only, since various changes and modifications within the spirit and scope of the invention will become apparent to those skilled in the art from this detailed description.
REFERENCES:
patent: 5933748 (1999-08-01), Chou et al.
patent: 6022781 (2000-02-01), Noble et al.
patent: 6084276 (2000-07-01), Gambino et al.
patent: 6222225 (2001-04-01), Nakamura et al.
patent: 6261920 (2001-07-01), Oyamatsu
patent: 6265777 (2001-07-01), Kobayashi
patent: 6342715 (2002-01-01), Shimizu et al.
patent: 6475865 (2002-11-01), Yang et al.
pa
Diaz José R.
Sharp Kabushiki Kaisha
Thomas Tom
LandOfFree
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