Interleaved arbitration scheme for interfacing parallel and seri

Details Interleaved arbitration scheme for interfacing parallel and seri Interleaved arbitration scheme for interfacing parallel and seri

1988-05-13

1991-04-02

Shaw, Gareth D.

Boots, shoes, and leggings

341100, 341101, 3649395, 364939, 36492792, 36492795, G06F 1300

Patent

active

050051512

ABSTRACT:
An arbitration circuit (10) is provided for selecting between a serial port (19) and a parallel port (21) for interface with a system port (17) having a system data bus (14) and a system address bus (16). A RAM (12) is supported by the buses (14) and (16). The arbiter (10) is operable to store a count value in an arbitration byte (38) which is addressable by the parallel port (21). The serial port (19) is operable to transfer data through a serial/parallel converter (30) to the system data bus (14) and system address bus (16) during a serial port access window. The parallel port (21) is allowed to access the system data bus and address bus at all other times. A count value indicating the duration of time before occurrence of the access window is stored in the arbitration byte (38) and is accessible by the parallel port and a parallel CPU (24) to determine when address and data information can be transmitted to the arbiter (10) for transfer to RAM (12). This provides an interleaved operation whereby the parallel port (21) can access the system during collection of data in the serial/parallel converter (30).

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