Semiconductor device manufacturing: process – Chemical etching – Combined with the removal of material by nonchemical means
Reexamination Certificate
2002-05-21
2004-12-14
Chen, Kin-Chan (Department: 1765)
Semiconductor device manufacturing: process
Chemical etching
Combined with the removal of material by nonchemical means
C438S700000, C438S720000
Reexamination Certificate
active
06831016
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to the manufacture of semiconductor devices, more particularly, to a method to prevent undesirable shorts between metal lines during the manufacture process of dynamic random access memory (DRAM).
2. Description of the Related Art
Chemical mechanical polishing (CMP) has been widely used in the fabrication of semiconductor devices such as dynamic random access memory for planarization of the surface of a semiconductor wafer. A variety of chemical reagent (i.e. slurry) is generally utilized to planarize an uneven insulating layer comprising borophosphate silicate glass (BPSG) by the chemical mechanical polishing process. This CMP slurry has polishing particles with high hardness so that a scratch is easily generated on the surface of BPSG. A conformal silicon oxide layer deposited by the subsequent step may thus have a dent or recess, which can trap conductive material, on the scratch. As a result, the trapped conductive materials can cause undesirable shorts between adjacent metal lines.
SUMMARY OF THE INVENTION
In view of the above disadvantages, an object of the invention is to provide a method to prevent electrical shorts between adjacent metal lines without alternation of the contact resistance of metal lines.
Accordingly, the above object is attained by the present inventive process, performed upon a semiconductor substrate having an insulating layer with a pair of damascene structures connecting to the semiconductor substrate and a scratch on the upper surface between the damascene structures. A diffusion barrier layer is deposited on the damascene structures and the scratch. Then, a metal layer is formed to fill the damascene structures. Next, the metal is chemical-mechanically polished to form a metal line. Furthermore, the diffusion barrier layer disposed on the surface of the scratch is removed by etching.
In an embodiment of the invention, the insulating layer is preferably silicon oxide by tetra-ethyl-ortho-silicate (TEOS). Also, the diffusion barrier layer preferably comprises titanium nitride, tantalum nitride or titanium/titanium nitride. Furthermore, the metal layer is preferably tungsten.
Moreover, in another embodiment of the invention, etching is preferably performed by reactive ion etching using an etching gas containing chlorine.
Furthermore, in another embodiment of the invention, the diffusion layer preferably has an etching selectivity of about 6:1 and about 7:1 with respect to the metal layer.
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Hsu Ping
Tsai Tzu-Ching
Chen Kin-Chan
Ladas & Parry
Nanya Technology Corporation
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