Semiconductor device manufacturing: process – Chemical etching – Combined with the removal of material by nonchemical means
Reexamination Certificate
2002-08-30
2004-12-14
Lee, Hsien Ming (Department: 2823)
Semiconductor device manufacturing: process
Chemical etching
Combined with the removal of material by nonchemical means
C438S692000, C438S694000, C438S745000, C438S751000
Reexamination Certificate
active
06831014
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor apparatus. More particularly, the present invention relates to a method of forming a copper wiring pattern in a semiconductor apparatus.
2. Description of the Related Art
The enlargement of a chip size and the miniaturization of a minimum machining dimension lead to the sharp Increase in parasitic capacitance and interconnect resistance caused by the wiring, which results in a wiring delay. As a method of solving it, an inter-level insulation film with a low dielectric constant is used for decreasing the parasitic capacitance. Also, a copper wiring with a small resistance is used for decreasing the interconnect resistance. Thus, the drop in the capacitance C through the low dielectric constant and the drop in a resistance R through the copper enable the reduction In the wiring delay (
∝
RC)
In order to drop the interconnect resistance, it is also important to drop an average wiring length. Since the average wiring length is inversely proportional to the number of wiring layers, a multi-level Interconnection technique is important for making the wiring into a multiple-layer configuration. To do so, a damascene wiring structure technique and a chemically mechanically polishing (CMP) technique become essential which can attain the multiple-layer configuration without involving the concave and convex portions on the surface of a lower layer.
The CMP is the step for precisely polishing a surface by using an abrasive material, in a process for manufacturing a semiconductor apparatus. It precisely flattens an upper portion of a lower layer so as not to form the concave and convex portions on an upper layer. The manufacturing step is the very fine step. Thus, the high technologies are required for an abrasive material, a polishing condition, a polishing apparatus, a washing method and the like.
The problems in the CMP of the conventional technique will be described below with reference to
FIGS. 1A
to
1
D.
FIGS. 1A
to
1
D is a section view showing a step of a CMP process in forming a damascene wiring. It shows a substrate
101
, an Insulation film
102
, a barrier film
103
, a wiring film
104
and a wiring trench
105
.
The substrate
101
is the substrate on which a semiconductor element, an inter-level insulation film, a damascene wiring and the like are formed. It may be a semiconductor substrate made of silicon, or a semiconductor substrate on which an insulation film made of silicon dioxide and silicon nitride is formed.
The insulation film
102
is the insulation film using an organic material such as a polymer of a hydrocarbon system or using an inorganic material such as silicon dioxide.
The barrier film
103
is a metallic thin film. It protects the inter-level insulation film
102
from being exposed to plasma, in the process, and also protects the wiring film
104
, from being diffused into an insulation film
102
. It is made of titanium nitride, tantalum and the like.
The wiring film
104
is the wiring film made of a metal having a low electric resistivity. It is formed in a wiring trench in the insulation film, and it functions as the damascene wiring. For example, it is made of copper.
Next, the manufacturing step will be described below with reference to
FIGS. 1A
to
1
D.
In
FIG. 1A
, the insulation film
102
is formed on the substrate
101
. Then, a wiring trench
105
is formed by using a photolithography process. After that, the barrier film
103
is deposited so as to cover an inner surface of the wiring trench
105
and the insulation film
102
. And then the wiring film
104
is formed on the barrier film
103
.
In
FIG. 1B
, the wiring film
104
is polished by carrying out a first polishing operation of CMP in which the barrier film
103
is used as a stopper. Consequently, the upper side of the wiring film
104
from the barrier film
103
is removed, and a surface of the barrier film
103
is exposed.
In
FIG. 1C
, a surface of the barrier film
103
and a surface of the wiring film
104
in the wiring trench
105
are rinsed through pure water. This rinsing operation washes the polishing solution of the CMP remaining on the surface.
In
FIG. 1D
, the barrier film
103
is polished by a second polishing operation of the CMP in which the insulation film
102
is used as a stopper. Consequently, the barrier film
103
and the wiring film
104
on the upper side from the insulation film
102
are removed, and a surface of said insulation film
102
is exposed.
However, in the step of
FIG. 1B
, the polishing operation of the CMP may cause slight pits
106
to be generated on the surface of the wiring film
104
. The pit
106
may be a case of etched pits caused by a chemically etching action or a case of a mechanical local damage caused by abrasive particles. These pits
106
are not removed even after a pure water rinsing step (FIG.
1
C), and it remains in its original state (pits
106
′). Then, in the second polishing step (
FIG. 1D
) of the CMP, it becomes larger pits
107
resulting from the chemically etching action or the mechanical damage.
In particular, the polishing solution used in the CMP sensitively reacts to a change in its concentration, pH and the like so that its property may be changed. It takes about one minute including the pure water rinsing step of
FIG. 1C
, until the start of the step of
FIG. 1D
after the completion of the step of FIG.
1
B. Meanwhile, if the polishing solution is not perfectly removed by the pure water rinsing step and even the slight solution remains on the wiring surface, the chemical property may be largely changed, including the effect of the pure water. In this case, a wiring metal or a protective film formed in the CMP on the wiring metal may be etched at a high etching speed that never appears in the usual usage. That is, there may be a case that even the pure water rinsing operation and the protective film can not prevent the generation of the pit
106
caused by the etching.
For example, since the wiring film
104
in the wiring trench
105
is formed on a narrow portion, a grain size is not very large. Thus, a rate of a grain boundary volume is high, which easily brings about a boundary etching, and results in a tendency that the pit
106
is easily generated. Hence, a technique is desired for suppressing the generation of the pit
106
caused by the etching and the like, on the surface of the wiring film
104
in the wiring trench
105
. The step of the pure water rinsing operation of the wiring film
104
in the CMP can not be carried out for a long time because of a relation to other processes, a throughput and a cost and the like. Hence, a technique is desired for suppress the etching on the wiring surface in a short time in the middle step of the CMP.
Even if the slight pit
106
is generated in FIG.
1
B and the polishing solution is not perfectly removed in
FIG. 1C
, a technique is desired for suppressing the increase of the pit
106
in the second polishing step of the CMP (
FIG. 1D
) and polishing and removing the pit
106
In the second polishing step. Also, the technique is desired for forming the damascene wiring in which a sectional area of wiring is constant, there is no dependency on a location, and a wiring resistance is small and stable.
In relation to the above-mentioned problems, Japanese Laid Open Patent Application (JP-A 2001-89747) discloses a polishing composition and a polishing method. The contents is as follows:
In this invention, a composition containing a benzotriazole derivative is used as the polishing composition when the CMP is carried out. The copper CMP is carried out by using the composition containing the benzotriazole derivative. Consequently, since a protective film is formed on a copper surface, the corrosion after the polishing operation is avoided. In addition, this provides the action for suppressing a copper film polishing speed.
Japanese Laid Open Patent Application (JP-A 2000-315666) discloses a method of manufactu
Lee Hsien Ming
NEC Electronics Corporation
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