Static information storage and retrieval – Floating gate – Multiple values
Reexamination Certificate
2002-11-20
2004-06-08
Nguyen, Tan T (Department: 2818)
Static information storage and retrieval
Floating gate
Multiple values
C365S185200, C365S185220
Reexamination Certificate
active
06747894
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a nonvolatile multilevel cell memory, and more particularly, to a technology for performing read operations and write operations with reliability.
2. Description of the Related Art
Nonvolatile semiconductor memories such as a flash memory store data by injecting electrons into the floating gates (or trap gates) of their memory cells to change the threshold voltages of the memory cells. The memory cells rise in threshold voltage when their floating gates contain electrons, and fall when the floating gates contain no electron.
Recently, flash memories that store a plurality of bits in each single memory cell have been developed in order to increase memory capacities.
FIG. 1
shows the distribution of the threshold voltages of memory cells in a four-level NAND type flash memory. The threshold voltages of the respective memory cells fall into any of areas L0, L1, L2, and L3 depending on the data programmed. The areas L0, L1, L2, and L3 correspond to 2-bit data “11”, “10”, “01”, and “00”, respectively. The memory cells of the area L0 have negative threshold voltages and operate as depletion transistors. The memory cells of the areas L1-L3 have positive threshold voltages and operate as enhancement transistors.
Data write (programming) is performed on each memory cell until the threshold voltage exceeds a verification voltage VV (VV1, VV2, VV3). For example, to write logic “10” to a memory cell, the programming operation is repeated until the memory cell exceeds the verification voltage VV1 in threshold voltage. Then, the threshold voltages of the respective memory cells are set to any of the areas L0-L3.
Data read is performed by comparing the threshold voltages of the memory cells with reference voltages VR (VR1, VR2, VR3). When a memory cell falls below the reference voltage VR1 in threshold voltage, the data retained in the memory cell is determined to be “11”. When a memory cell lies between the reference voltages VR1 and VR2 in threshold voltage, the data retained in the memory cell is determined to be “10”. When a memory cell lies between the reference voltages VR2 and VR3 in threshold voltage, the data retained in the memory cell is determined to be “01”. When a memory cell exceeds the reference voltage VR3 in threshold voltage, the data retained in the memory cell is determined to be “00”.
A reference voltage (conduction voltage) VR4 is supplied to unselected memory cells and selecting transistors to be described later. The reference voltage VR4 is set with a sufficient margin from the area L3.
FIG. 2
shows an overview of a memory cell array of the four-level NAND type flash memory.
The memory cell array comprises a plurality of blocks BLK (BLK
0
, BLK
1
, . . . ) and page buffers having sense amplifiers SA. Each block BLK has a plurality of memory cell strings STR. The memory cell strings STR are composed of a plurality of memory cells that are connected in series between selecting transistors. The memory cells have a control gate and a floating gate. Each memory cell is connected at its control gate to a word line WL. The gates of the selecting transistors are each connected to a selecting line SG. Each memory cell string STR is connected at both ends to a bit line BL and a control line ARVSS.
Write operations on the memory cells are performed by supplying a high voltage to word lines WL corresponding to the memory cells to be written and supplying a low voltage to a bit line BL so that electrons are injected to the floating gates of the memory cells through the channels.
Read operations on the memory cells are performed by supplying a reference voltage VR (any of VR1, VR2, and VR3) to word lines WL (for example, WL10 and WL11) corresponding to the memory cells to be read (for example, the circled ones in the diagram), supplying the reference voltage VR4 to the other word lines WL and the selecting lines SG, and supplying a ground voltage to the control line ARVSS. When memory cells to be read exceed the reference voltage VR in threshold voltage, no channel is formed in the memory cells. In this case, no current flows from the bit lines BL to the control line ARVSS. When memory cells to be read fall below the reference voltage VR in threshold voltage, channels are formed in the memory cells and thus currents flow from the bit lines BL to the control line ARVSS. The sense amplifiers SA compare the currents flowing through the bit lines BL with reference currents to determine whether the threshold voltages are higher than the respective reference voltages VR. Then, the logical values of the data stored in the memory cells are determined.
Erase operations on the memory cells are performed by supplying a low voltage to the control gates of the memory cells to be erased and supplying a high voltage to the well regions of the memory cells so as to emit the electrons stored in the floating gates. Here, the control gates of the memory cells not to be erased are rendered floating, for example.
To store multilevel data in a single nonvolatile memory cell, a plurality of reference voltages VR (VR1-VR3) must be each located in between the distributions (L0-L3) of the threshold voltages as shown in FIG.
1
. On this account, multilevel memory cells get considerably smaller in read margin as compared to binary memory cells which have a single reference voltage. Consequently, when variations of the semiconductor fabrication process change the write characteristics of the memory cells and shift the distributions L1-L3, insufficient read margins can possibly cause defects.
FIG. 3
shows the distributions of the threshold voltages for situations where the memory cells change in write characteristics. In the diagram, the distributions shown by the broken lines are the normal ones shown in FIG.
1
.
For example, if the rates of change of the threshold voltages to write voltages increase due to variations of the fabrication process, the distributions L1-L3 range wider. As a result, a difference between the maximum value in the distribution L1 of the threshold voltages corresponding to logic “10” and the reference voltage VR2 (read margin for logic “10”) decreases. Similarly, a difference between the maximum value in the distribution L2 of the threshold voltages corresponding to logic “01” and the reference voltage VR3 (read margin for logic “01”) decreases. In particular, when the distribution L2 ranges wider as shown in the diagram, the read margin for logic “01” might practically disappear.
Generally, semiconductor products vary in chip characteristics depending on the positions of the chips on wafers, the positions of the wafers in fabrication lots, and the fabrication lots. For this reason, decreases in read margins can cause a drop in yield. The lower yield in turn can increase the fabrication cost.
SUMMARY OF THE INVENTION
It is an object of the present invention to secure operating margins of a nonvolatile multilevel cell memory in order to enhance a fabrication yield.
According to one of the aspects of the nonvolatile multilevel cell memory of the present invention, the cell memory has electrically-rewritable nonvolatile multilevel memory cells. A programming voltage generator generates a plurality of programming voltages to change threshold voltage in each of the memory cells according to logic of write data. A first memory unit stores a plurality of reference values respectively corresponding to a plurality of reference voltages for judging the threshold voltages of the memory cells. At least one of the reference values stored in the first memory unit is rewritable. A reference voltage generator generates the reference voltages, respectively, according to the reference values stored in the first memory unit, when reading data from the memory cells.
Since the reference value(s) for generating the reference voltage(s) is/are rewritable, the reference values can be modified in accordance with the characteristics of the memory cells evaluated in advance. That is, the reference voltages can be change
Arent & Fox PLLC
Fujitsu Limited
Nguyen Tan T
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