Arithmetic apparatus with overflow correction means

Details Arithmetic apparatus with overflow correction means Arithmetic apparatus with overflow correction means

1994-11-10

1996-04-16

Malzahn, David H.

Boots, shoes, and leggings

G06F 1100

Patent

active

055089518

ABSTRACT:
An arithmetic apparatus includes an arithmetic logic unit for performing a given arithmetic operation of double precision data having a preselected number of bits, a first register storing results of the arithmetic operation of higher-order bits in the double precision data, a second register storing results of the arithmetic operation of lower-order bits in the double precision data, an overflow-detection circuit for detecting overflow conditions of the results of the arithmetic operations, a maximum/minimum value-setting circuit for setting the results of the arithmetic operation to be stored in the first register to one of maximum and minimum values according to the overflow conditions, and a correction circuit for correcting an output value indicative of he results of the arithmetic operation provided by the second register to one of a first value defined by a bit sequence of 0s and a second value defined by a bit sequence of 1s according to the overflow condition.

REFERENCES:
patent: 4945507 (1990-07-01), Ishida et al.

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