Circuit and method for detecting if a sum of two multibit number

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364787, G06F 700

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active

055089500

ABSTRACT:
A circuit and method for detecting if a sum of a first multibit number A of N bits and a second multibit B of N bits equals a third multibit number C of N bits prior to availability of the sum of A and B. A propagate signal, a generate signal and a kill signal are generated for each bit in the proposed sum. A zero signal is formed from these signals. The particular manner of formation of the zero signal for each bit depends upon the state of the third multibit number C for the corresponding bit and the prior bit. The zero signal is an exclusive OR of the corresponding propagate signal P.sub.n and a kill signal K.sub.n1 of a prior bit if the current bit and the prior bit of C are "00". The zero signal is an exclusive NOR of the corresponding propagate signal P.sub.n and a generate signal G.sub.n-1 of a prior bit if the current bit and the prior bit of C are "01". The zero signal is an exclusive NOR of the corresponding propagate signal P.sub.n and a kill signal K.sub.n-1 of a prior bit the current bit and the prior bit of C are "10". The zero signal is an exclusive OR of the corresponding propagate signal P.sub.n and a generate signal G.sub.n-1 of a prior bit if the current bit and the prior bit of C are "11". The sum of A and B equals C if all the zero signals are active "1". The propagate signal, generate signal and kill signal of the various bits can be used to from the sum. This technique provides the equality signal before the carry of the sum can ripple through the addition.

REFERENCES:
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patent: 4815019 (1989-03-01), Bosshart
patent: 4831570 (1989-05-01), Abiko
patent: 4924422 (1990-05-01), Vassiliadis et al.
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patent: 5095458 (1992-03-01), Lynch et al.
IBM Technical Disclosure Bulletin vol. 30, No. 11, Apr. 88, pp. 288-290.

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