Electricity: measuring and testing – Fault detecting in electric circuits and of electric components – Of individual circuit component or element
Reexamination Certificate
2002-06-04
2004-08-03
Tang, Minh N. (Department: 2829)
Electricity: measuring and testing
Fault detecting in electric circuits and of electric components
Of individual circuit component or element
C324S765010, C324S1540PB, C714S724000
Reexamination Certificate
active
06771087
ABSTRACT:
TECHNICAL FIELD OF THE INVENTION
The present invention is directed, in general, to testing integrated circuits and, more specifically, to isolating and testing individual modules within an integrated circuit.
BACKGROUND OF THE INVENTION
An integrated circuit (IC) typically consists of large numbers of interconnected digital and/or analog elements. (e.g., logical gates, communication circuitry, memories, etc.) for carrying out predetermined operations. Recent advances in fabrication technology have made it possible to integrate a plurality of circuitry of different functionality into a single chip. Such implementations are usually known as System-On-a-Chip (SOC). Each circuitry, usually called a module, is designed as an independent unit having its power supply, input and output lines.
In a typical SOC development, a separate team of hardware designers designs each module. A verification team specifies and develops tests and tools, for verifying the SOC. The verification tests guaranties that the IC has been manufactured correctly and performs as expected according to simulations. However, because of the relative limitations of packaging technology, only a comparatively limited number of primary input and primary output pins (I/O pins) are provided for the testing of an integrated circuit.
Usually, each module is imported from a different team, and integrated into the SOC. Part of the design of the SOC concerns integrating adequate testing features for testing the module in the SOC. It is therefore mostly desired to exploit the modules' existing testing tools, and testing environments, of each module, and integrate them into the SOC testing environment. To utilize the existing testing infrastructure of each module for the testing of the SOC, some additional hardware is integrated to enable an efficient isolation of each of the module's input/output (I/O) lines from other operating modules, and apply a verification test compatible to its environment.
When testing the chip's modules at a “stand alone” mode, the I/O lines of the module are isolated to prevent interference that may originate at other operating modules attached to the tested module. The verification is actually conducted by applying a set of test vectors (various combinations of possible Input signals) to the inputs of the module and monitoring the output signals resulting from these signals. The expected responses resulting from a set of known input patterns can be generated based on the intended function (and/or operation) of the circuitry (functional testing). A successful verification is one in; which the output patterns that are obtained corresponding to a set of known input patterns, match the expectations according to simulations or the designated functionality of the module.
However, since the access to the module's I/O lines is usually limited, and since the verification hardware should not affect the normal functionality of the chip (i.e, in its active mode), special attention is, required to design the additional testing circuitry involved in such tests. One method for obtaining verification test results is schematically illustrated in FIG.
1
. In this example, the output lines of the modules
101
,
102
, and
103
, are connected to the chip's output port
105
through a multiplexer (MUX)
104
.
The MUX
104
in this case acts as an arbitrator, which is utilized to direct the output line of the tested module to the chip's output port
105
. In a similar fashion, the MUXs
321
,
322
, and
323
are utilized to select the active input of each module. Each one of the MUXs
321
,
322
, and
323
is provided with a functional signal (i.e., the input signal utilized while the module is in its normal operation mode) and the test bus signals on
307
. The arbitration unit
305
produces a control signal on lines
331
-
333
, which are utilized by the MUXs to select the appropriate signal for their output.
Such methods are efficiently implemented with relatively little additional circuitry, and control signals. However, since each module's output is directed to the output port
105
through the MUX
104
, this type of testing circuitry is substantially costly in terms of the lengths of the conducting lines used, and therefore also in chip area consumption. Typically the MUX is located near the IC's port resulting in the waste of long output lines drawn from each module's output towards the MUX Inputs. Other disadvantages of such methods are expressed in extra delays, which are added to the functional signal that has to pass through the MUX.
In a typical IC, each of the modules has I/O consisting of a plurality of conducting lines. It is therefore an important necessity to struggle to provide efficient testing means utilizing I/O testing lines that are as short as possible.
Another attitude for conducting verification test to ICs is known as the “Boundary-Scan Architecture” (IEEE t (Standard 1149.1), developed by the Joint Test Action Group (JTAG). The JTAG group developed a testing method based on the concept of a serial shift register positioned around the boundary of the tested device. This concept resembles the so-called “bed-of-nails” technique that was the customary testing technique of printed circuits in the mid-1970s.
FIG. 2
schematically illustrates the boundary-scan testing method developed by the JTAG group. Each of the modules
101
,
102
and
103
is equipped with supplementary “boundary scan cells” (hereinafter referred to as “scan cells”),
201
a
-
201
f
,
202
a
-
202
f
, and
203
a
-
203
f
, that are located on the boundaries of each module. Each scans cell is a multi-purpose memory element capable of performing “shift-in,” “shift-out,” “update,” and “capture” operations. In this fashion, particular tests can be applied. to the device interconnects through the scan path formed by serially connecting the scan cells in the form of a chain.
Some of the scan cells are utilized to input test signals to the module, others to capture the module's output signals. For instance, module B
102
is equipped with scan cells
202
a
-
202
c
which are utilized to introduce test patterns to the module, and scan cells
202
d
-
202
f
to collect the output signals resulting from those input signals.
This architecture allows the testing of each module in its functioning environment. However, it is time consuming and cumbersome, especially when there are a substantial number of modules to test. As an example, let us suppose that a test pattern should be applied to module B
102
. In such a case, the test patterns should be applied via the input port
207
, and travel towards module B's input scan cells
202
a
-
202
f
by performing a serial shift of the scan cells, i.e., passing the signals through module A's scan cells
201
a
-
201
f
. Similarly, the resulting output pattern stored in the module's output scan cells
202
d
-
202
f
will reach the output port
208
by serially shifting the signals along the scan path through module C scan cells
203
a
-
203
f.
As will be appreciated by skilled artisans, the test logic that is involved in boundary-scan tests is complex. More precisely, such test logic involves full control of the modules' clock(s) (the clock is stopped during shift-in and shift-out, and single stepped in between). As a result the testing is not run in real time, and the “stand alone” tests and testing environment need to be converted.
Another testing technique is disclosed in U.S. Pat. No. 5,936,976, and schematically illustrated in FIG.
3
. This method utilizes switching devices to select the output signal, and multiplexers to select the input signal of the module to be tested. In the drawing, switching devices
211
,
212
, and
213
are utilized to select the output signal of the tested module. Similar to what was described hereinabove, in order to select the output signal of one of the modules
101
,
102
, or
103
, the respective switch device is activated (switched to its conducting state), and the other switches deac
Mizrahi Abraham
Oz Oved
Advanced Micro Devices , Inc.
Tang Minh N.
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