Level shift circuit and semiconductor integrated circuit

Details Level shift circuit and semiconductor integrated circuit Level shift circuit and semiconductor integrated circuit

2001-10-15

2004-08-10

Nguyen, Minh (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Amplitude control

C327S112000, C326S063000, C326S083000

Reexamination Certificate

active

06774695

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor integrated circuit and to a level conversion circuit, and more particularly, for instance, to a technology which can be effectively used for an interface circuit for a semiconductor integrated circuit in which the amplitude of internal signals and that of external signals differ from each other.
According to the prior art, circuits for converting signals of a smaller amplitude into signals of a greater amplitude include, for instance, a level conversion circuit disclosed in Japanese Patent Laid-Open No. Hei 5 (1993)-343979, the circuit illustrated in FIG.
10
. The circuit of
FIG. 10
consists of an inverter INV
0
, having VDD (e.g. 1.5 V) as its source voltage, for inverting an input signal IN and a latch circuit LT, having VDD
2
higher than VDD (e.g. 3.3 V) as its source voltage and the signal/IN resulting from inversion by the inverter and the pre-inversion signal IN. The latch circuit LT has a configuration comprising one CMOS inverter INV
1
in which two p-channel MOSFETs Qp
1
and Qp
2
and one n-channel MOSFET Qn
1
are connected in series and one CMOS inverter INV
2
in which two p-channel MOSFETs Qp
1
and Qp
3
and one n-channel MOSFET Qn
2
are connected in series, the output terminal of each inverter being connected to the gates of the MOSFETs Qp
2
and Qp
3
of the other inverter.
SUMMARY OF THE INVENTION
In the level conversion circuit of
FIG. 10
, when the input signal IN of 0 to 1.5 V in amplitude rises from a low level to a high level, the MOSFET Qn
1
immediately shifts from an off-state to an on-state. As a result, its output signal OUT varies from VDD
2
, which may be 3.3 V for instance, to a ground potential (0 V), but when the input signal IN varies from a high level to a low level, only when the MOSFET Qn
2
is turned on by the inverted signal/IN to vary the output of the inverter INV
2
to a low level and the MOSFET Qp
2
shifts from an off-state to an on-state, the output signal OUT varies from the ground potential (0 V) to VDD
2
, which may be 3.3 V.
For this reason, a level conversion circuit according to the prior art is slower in the variation of the output signal from a low level to a high level than in the variation from a high level to a low level. As a result, on the part of a circuit to receive a signal from such a level conversion circuit, the signal should be accepted at the later signal timing, resulting in the problems of more complex timing design and of a longer time taken by signal transmission, which impedes raising the system speed.
An object of the present invention is to provide a level conversion circuit whose output signal varies from a low level to a high level and from a high level to a low level substantially as fast.
Another object of the invention is to provide a semiconductor integrated circuit technology which makes it possible to raise the speed of signal transmission in a semiconductor integrated circuit having within it two signal transmission routes differing in amplitude.
Still another object of the invention is to make it possible to raise the speed of a system using a semiconductor integrated circuit having a level conversion circuit in its input/output (I/O) unit and forming and supplying a large amplitude signal on the basis of a narrow amplitude internal signal.
The above-noted and other objects and novel features of the invention will become more apparent from the description in this specification when taken in conjunction with the accompanying drawings.
What follows is a brief summary of typical aspects of the present invention disclosed in this application.
Thus, the configuration is such that a level conversion circuit is composed of a level shift circuit for supplying a level-converted signal in the same phase as the input signal and a signal in the reverse phase thereto and a follow-up circuit responsive to the earlier of the output signals of the level shift circuit for generating an output signal, wherein the follow-up circuit consists of an inverter circuit in which two p-channel type MOS transistors and two n-channel type MOS transistors are connected in series between a first voltage terminal and a second voltage terminal, of which one pair is used as input transistors and the remaining pair of transistors are subjected to control based on the output signal of the level shift circuit to be quickly responsive to the next variation.
A level conversion circuit according to a first aspect of the invention under the present application has a first circuit comprising a first input terminal for receiving a first signal having a first signal amplitude, a first output terminal for supplying a second signal having a second signal amplitude greater than the first signal amplitude and being in the same phase as the first signal, and a second output terminal for supplying a third signal having a second signal amplitude greater than the first signal amplitude and being in the phase reverse to the first signal; and a second circuit comprising a first p-channel type MOS transistor, a second p-channel type MOS transistor, a first n-channel type MOS transistor and a second n-channel type MOS transistor whose source-drain routes are connected in series between a first voltage terminal and a second voltage terminal and the drain of the first p-channel type MOS transistor and the drain of the n-channel type MOS transistor are connected to a third output terminal, wherein the second circuit forms a fourth signal having the second signal amplitude on the basis of the signal variation of the second signal supplied from the first output terminal of the first circuit or of the third signal supplied from the second output terminal of the first circuit, whichever is faster in signal level change, and supplying the fourth signal from the third output terminal.
The above-described means, as the second circuit forms an output signal on the basis of what is faster in signal level change out of the complementary signals supplied from the first circuit, the output signal can quickly vary not only at the leading edge but also the trailing edge of the input signal, and a signal having a small amplitude can be converted into one of a large amplitude and transmitted without sacrificing the signal transmission speed.
Preferably, a delay means may be provided to delay the second signal supplied from the first output terminal of the first circuit or the third signal supplied from the second output terminal of the first circuit to control the second p-channel type MOS transistor and the first n-channel type MOS transistor, or the first p-channel type MOS transistor and the second n-channel type MOS transistor. This results in shifting of the second circuit to a state in which it is more quickly responsive to the next signal change and thereby makes it possible to raise the signal transmission speed.
In a further proposed configuration, where a circuit from which, according to a signal inputted to the gate terminal of a MOS transistor, a signal matching the gate input signal is supplied to the source or drain terminal of the MOS transistor is defined to be one stage, the number of circuit stages which a signal reaching the third output terminal of the second circuit from the first input terminal of the first circuit via the second output terminal goes through and the number of circuit stages which a signal reaching the third output terminal of the second circuit from the first input terminal of the first circuit via the third output terminal goes through are equal. This substantially equalizes the lengths of time taken by the signal in the same phase as the input signal and the signal in the reverse phase to the input signal to reach the second circuit, enabling the output signal to quickly vary not only at the leading edge but also the trailing edge of the input signal and the transmission speed of signals having different amplitudes to be raised.
Further, the second circuit may be so configured that the state of the second p-channel type MOS transistor or the firs

Affiliated with

Also associated with

Rating

Level shift circuit and semiconductor integrated circuit does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Level shift circuit and semiconductor integrated circuit, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Level shift circuit and semiconductor integrated circuit will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3305526