Coded data generation or conversion – Analog to or from digital conversion – Differential encoder and/or decoder
Reexamination Certificate
2003-08-05
2004-06-29
Young, Brian (Department: 2819)
Coded data generation or conversion
Analog to or from digital conversion
Differential encoder and/or decoder
C331S00100A, C375S376000, C332S127000
Reexamination Certificate
active
06756927
ABSTRACT:
BACKGROUND OF THE INVENTION
Field of the Invention
The invention relates to a sigma-delta programming device for a PLL frequency synthesizer, a configuration using the sigma-delta programming device, a PLL frequency device, and a method for programming a programmable device.
Sigma-delta modulators are known in digital technology. Due to their transfer characteristic (all-pass filter for the input signal, high-pass filter for the quantization noise), they are used in conjunction with a programmable frequency divider for direct or indirect modulation of an analog transmission signal. These technologies have a broad scope of application and are used, by way of example, in the DECT (Digital European Communications Transmission) standard or in Bluetooth systems.
Indirect modulation involves the use of a PLL (Phase Locked Loop) circuit as a modulator. PLL circuits have a high level of flexibility with regard to usable reference frequencies for a demanded frequency resolution at the output of the PLL circuit, and afford short settling times. Modulation is performed using a programmable frequency divider that is disposed in the feedback path of the PLL circuit and is actuated or programmed by a programming device on the basis of a modulation signal. Preferably, “fractional-N PLL circuits” are used. Fractional-N PLL circuits allow frequency division by N, where N does not necessarily have to be an integer (“fractional synthesis technology”). In the case of fractional synthesis technology, the interference arising upon integer division in a PLL as a result of lateral lines in the spectrum is circumvented.
Programming devices for fractional-N PLL circuits are already known that contain a sigma-delta modulator.
U.S. Pat. No. 4,965,531 to Riley describes a fractional-N PLL frequency synthesizer. Fractional frequency division is effected by a one-bit sigma-delta programmer of second or higher order that actuates a single-stage dual-modulus frequency divider or, in another exemplary embodiment, a two-stage multi-modulus frequency divider. In addition, the specification mentions that the sigma-delta programmer can also have a multi-bit output.
U.S. Pat. No. 6,008,703 to Perrott et al. specifies a further fractional-N PLL frequency synthesizer. The circuit includes a fractional frequency divider that includes a sigma-delta modulator as a programming device and a multi-modulus frequency divider in the feedback loop of the PLL circuit. The sigma-delta modulator produces a divider signal having a word length of six bits. The multi-modulus frequency divider includes a multi-modulus 4/5/6/7 divider stage having an input for two bits and four cascaded ⅔ divider stages that each have a single-bit input. This permits frequency division to be achieved that corresponds to “swallowing” a number of between 0 and 63 periods (2&pgr;) of the output signal from the voltage-controlled oscillator (pulse-swallowing principle).
German Published, Non-Prosecuted Patent Application No. DE 199 29 167 A1 describes two-point modulation using a PLL circuit. The modulation is performed firstly using a sigma-delta fractional-N frequency divider in the feedback path of the circuit and secondly by supplying the modulation signal (which has been subjected to analog conversion beforehand) at a summation point at the input of the voltage-controlled oscillator.
U.S. Pat. No. 6,044,124 to Monahan et al. describes a sigma-delta programming device for a programmable frequency divider. The sigma-delta programming device includes a unit having a sigma-delta modulator, a dither function modulator and a switch that is controlled by the output signal from the dither function modulator and delivers a control signal for the fractional component of the frequency division. An adder adds this control signal for the fractional component of the frequency division to a control signal for the integer divider component. The output signal from the adder is used to program the programmable frequency divider.
The frequency-limiting element in such a PLL circuit is the frequency divider. This applies particularly if the frequency divider is in the form of an integrated component in a pure CMOS process. In this context, it should be remembered that, in relation to frequency limiting, the use of uneven divider factors (divisors) for programming the frequency divider is far more critical than the use of even divisors. Attempts are therefore made to prevent the occurrence of uneven divisors for actuating a programmable frequency divider. To date, it is possible to produce exclusively even divisors only if the programming device for actuating the frequency divider is constructed from multi-bit sigma-delta modulators of complicated configuration that include a comparator having a plurality of decision thresholds. This requires a high level of involvement for layout and manufacture.
SUMMARY OF THE INVENTION
It is accordingly an object of the invention to provide a sigma-delta programming device for a PLL frequency synthesizer, a configuration using the sigma-delta programming device, a PLL frequency device, and a method for programming a programmable device that overcome the hereinafore-mentioned disadvantages of the heretofore-known devices of this general type and that produce, in a simple manner, only even output values (divisors) for programming a device such as a programmable frequency divider. In addition, the invention is also aimed at specifying configurations of simple construction for direct and indirect modulators.
With the foregoing and other objects in view, there is provided, in accordance with the invention, a sigma-delta programming device, including an input, a sigma-delta modulator, an adder, and a multiplier. The input is configured to receive a digital signal with a word length of N bits, most significant L bits of a data word representing places before a decimal point in a binary number represented by the data word, and remaining N−L less significant bits representing places after the decimal point in the binary number. The sigma-delta modulator is configured to receive N−L+1 less significant bits of the N-bit data word. The adder has a first adder input configured to receive the L−1 most significant bits of the N-bit data word, a second adder input being configured to receive a signal processed by the sigma-delta modulator, and an output. The multiplier is configured to multiply the output of the adder by two.
The fact that the sigma-delta modulator is supplied not only with the N−L less significant bits that represent the places after the decimal point in the data word in the modulation signal but also with the bit in the least significant place in front of the decimal point in this data word means that rightward shifting of the integer component of the data word by one binary place and hence multiplication thereof by the factor 0.5 are achieved. On account of the one additional place, the resolution of the sigma-delta modulator needs to be one bit greater than in the case of a sigma-delta modulator based on a conventional implementation. Following addition of the data word's integer component shifted one place to the right (and shortened by its least significant bit) to the output of the sigma-delta modulator in the adder, it is multiplied by the value 2. This converts the data word back to the correct value range and also ensures that the divisor delivered at the output of the multiplier is always an even integer.
Preferably, the sigma-delta modulator is a sigma-delta modulator that is constructed exclusively from single-bit decision makers (a comparator having just one decision threshold). This achieves minimal layout and implementation involvement for the sigma-delta programming device.
One preferred application of the inventive sigma-delta programming device is to use it to actuate a programmable frequency divider that is situated in the feedback loop of a PLL circuit. This ensures that even-numbered divisor values (the output values from the sigma-delta programming device) are used for
Hammes Markus
Van Waasen Stefan
Greenberg Laurence A.
Infineon - Technologies AG
Locher Ralph E.
Nguyen John B.
Stemer Werner H.
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