Integrated CPU and DMA with shared executing unit

Details Integrated CPU and DMA with shared executing unit Integrated CPU and DMA with shared executing unit

1989-03-20

1991-04-02

Lee, Thomas C.

Boots, shoes, and leggings

3642423, 364249, 3642492, 3642395, 3642446, 364238, 3642381, 364240, 36424231, G06F 922, G06F 1578, G06F 1200

Patent

active

050051210

ABSTRACT:
A data processor controller for a microprogramming system is constructed with a single operation execution unit serving both a microprocessor and a peripheral device such as a direct memory access controller. In addition to the single operation execution unit, the controller includes a micro-memory which stores micro-instructions for controlling both the microprocessor and the peripheral device, and address registers, multiplexers and decoders integrated into a single device. Different ROM address registers in the controller are separately assigned to provide an address decoder with addresses of selected memory locations in the micro-memory containing the micro-instructions for the microprocessor and the peripheral device, thereby enabling the controller, through multiplexing between the address registers, to use the arithmetic execution unit, counter and bus interface of the single operation exeuction unit on a time sharing basis, for controlling the functions of both the microprocessor and the peripheral device.

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"Nikkei Electronics", No. 296 pp. 129-158 Direct Memory Access Controller, Nikkei McGraw-Hill. C.C. Aug. 1982.

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