Voltage regulator

Details Voltage regulator Voltage regulator

2003-05-30

2004-12-07

Han, Jessica (Department: 2838)

Electricity: power supply or regulation systems

Output level responsive

Using a three or more terminal semiconductive device as the...

C323S225000, C323S315000, C323S285000

Reexamination Certificate

active

06828766

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to voltage regulators, and more particularly to a voltage regulator capable of quickly restoring the normal functioning mode after an abrupt load variation during a stand-by state.
BACKGROUND OF THE INVENTION
Switching regulators include one or more power switches, components capable of storing energy (inductor and capacitor) and a control circuit, generally including both analog and digital circuits, for driving the power switch(es) to nullify or reduce the error between the output voltage of the regulator and a reference voltage. In certain applications (e.g. in battery powered devices) a high efficiency of the regulator even under low load conditions is important. At low loads the power consumption of the regulator is substantially due to the control circuit, both by the digital and analog stages, because power dissipation in the power switch(es) is negligible. The current absorbed by the logic driving circuit, for loading the capacitance(s) of the control input of the switch(es), is proportional to the switching frequency, while the consumption of the analog portion of the control circuit is substantially independent from the frequency.
To improve the efficiency under low load conditions, it would be necessary to reduce the switching frequency and the power dissipation of the analog stages. Constraints on the size of inductors and capacitors impose the choice of a relatively high switching frequency and the dissipation of the analog blocks cannot be reduced beyond a certain limit, otherwise performance would be excessively penalized. Many architectures of controllers implementing a specific low load functioning mode, different from that used at high load conditions, have been proposed, for modifying the operating parameters. The known approaches that are discussed hereinbelow refer to a current-mode regulator such as that depicted in FIG.
1
. The converter may be, for instance, a buck converter, comprising a HS switch and eventually a second LS switch, working as a synchronous rectifier, with a dedicated comparator ZERO_CROSSING COMP for detecting and signaling the zero crossing of the current in the inductor of the control circuit, to make the latter prevent the current in the coil from inverting its direction.
The current mode controller comprises a first feedback loop that makes the current in the inductor equal to a certain programmed value. A second feedback loop (voltage loop) determines the programmed current in function of the integral of the error voltage, to which an eventual proportional contribution is added. Typically, the voltage loop is composed of an error amplifier G
M
(commonly a transconductance amplifier) and an integration capacitance C
COMP
, defining an integrator, optionally with a compensation resistance R
COMP
in series thereto when a proportional contribution is required. Usually, the transconductance amplifier is capable of outputting a relatively low maximum current (in terms of absolute value) and proportional to the absorbed current, which on its turn does not depend on the voltage error (because the amplifier is a class A amplifier).
The current loop includes current sensing means/unit, represented by a circular dial on a terminal of the inductor, and by a comparator CURRENT COMPARATOR that compares a voltage proportional to the current in the inductor (for example, the voltage drop on a sensing resistor connected in series with the inductor or alternatively on the HS switch when it is on), with the output voltage of the transconductance amplifier that may be attenuated if needed. A clock signal, generated by an oscillator OSCILLATOR, switches on the switch HS while the comparator switches it off when the current flowing in the coil reaches the programmed value. A further ramp signal generated by the circuit SLOPE GEN is input to the comparator for ensuring the stability of the current loop when the duty-cycle is greater than 0.5.
The voltage loop is stable when the overall transfer function G
LOOP
(s) between the current in the inductor and the programmed current has a certain shape (appropriate cross frequency and phase margin) independently from the capacitance and the parasitic series resistance ESR of the output capacitor C
OUT
. This implies an appropriate choice of the capacitance C
COMP
and of the compensation resistance R
COMP
. In general, a compensation resistance is required when the zero frequency of the output capacitance
f
OUT
=
1
2
⁢
π
·
C
OUT
·
ESR
(
1
)
is very high.
A known technique for improving efficiency at low load includes making the regulator function in burst mode when the load current drops below a certain burst threshold. Each burst may be constituted by a plurality of pulses of the same frequency at which the regulator would be functioning with a load greater than the threshold, or, even, by a single pulse. In case there are more pulses, their number may be fixed or variable with the load.
In the interval between a burst and the successive one, the current in the inductor becomes null. The (average) current in the inductor during a burst must be at least equal to the current delivered to the load. Between a burst and the successive one, some of the analog circuits may be turned off, so that the effective average consumption of the controller diminishes when the load decreases. At null load conditions, only the analog blocks that cannot be turned off absorb a current, such as the reference voltage generator, and the components necessary to restore the switching activity.
When the burst is constituted by a single pulse, that is the current in the coil has a triangular waveform, the current peak must be at least twice the burst threshold I
BURST
. When there are more pulses in a burst, the greater the number of pulses, the smaller each current peak may be than twice the burst threshold I
BURST
. If each current peak is made equal to the burst threshold I
BURST
, the system must be capable of varying the number of pulses of the burst in function of the load. At low load conditions there will be few pulses, while when the load increases and approaches the threshold there will be longer lasting bursts. This second mode is less noisy than the approach contemplating a single pulse because of the smaller peak current and for this reason it is often preferred.
A way for implementing a variable duration burst mode under low load conditions is depicted in
FIG. 2. A
hysteresis comparator SLEEP COMPARATOR compares the output of the integrator that is proportional to the programmed current, with a threshold corresponding to the load current below which the burst mode functioning starts. The stand-by signal SLEEP generated by the comparator SLEEP COMPARATOR sets (when active) the regulator in stand-by, whereby the power switch HS and various analog circuits are turned off, among which the oscillator, the current comparator and the slope compensation circuit SLOPE GEN. If a second switch LS is present, this is turned on and remains on as long as the current in the inductor is positive, and it is turned off when the current becomes null. The integrating circuit and the reference voltage generator must remain on, instead.
As shown in
FIG. 3
, during each burst, the current in the coil is close to the burst current and the peak of each pulse varies in the range comprised between the upper I
MAX
and lower threshold I
MIN
of the comparator. Between a burst and the successive one, the current becomes null. The voltage of the integrator oscillates about the two thresholds of the sleep comparator and the output voltage oscillates about the reference voltage. The amplitude of the positive and negative over-elongations of the output voltage depends on the separation between the two thresholds, on the output capacitance and on its time constant ESR*C
OUT
and on the capacitive branch R
COMP
−C
COMP
of the integrator.
The drawback of this known approach is the delay of response to a load transient. When the stand-by interval is long (very small

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