Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Of specified configuration
Reexamination Certificate
2003-01-21
2004-12-14
Potter, Roy (Department: 2822)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Of specified configuration
C257S701000
Reexamination Certificate
active
06831368
ABSTRACT:
CROSS-REFERENCE TO RELATED APPLICATIONS
This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2002-13438, filed Jan. 22, 2002; the entire contents of which are incorporated herein by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device and a method of manufacturing the same. More particularly, the invention relates to a technique of using a low dielectric-constant insulating film as an interlayer insulating film.
2. Description of the Related Art
It is proposed that insulating films having lower relative dielectric constants than ordinary SiO
2
films be used as interlayer insulating films in LSIs. The use of low dielectric-constant insulating films can lower inter-wiring capacitances, making it possible to enhance the operating speed of the LSI.
Most low dielectric-constant insulating films are, however, softer and more fragile than ordinary SiO
2
films. They are likely to be deformed, scratched or cracked. When used as interlayer insulating films in any LSI, too, they may be deformed or cracked when pads are connected to an external portion, inevitably decreasing the reliability or yield of the LSI. More specifically, they may be deformed or cracked when they receive a pressure as a test probe pressed onto the pads to evaluate the characteristics of LSI elements or as wire bonding is performed to connect the pads to an external portion.
To solve this problem, an insulating film made of ordinary SiO
2
may be formed in the peripheral region of a semiconductor chip, where the pads are provided, and a low dielectric-constant interlayer insulating film may be formed in the circuit region inside the peripheral region, where transistors, wires and the like are provided.
Pads are formed on the interlayer insulating films that lie, one above another, in the peripheral region of the chip. The pads formed on each interlayer insulating film are connected to the pads formed on the next interlayer insulating film by conductive portions (vias) that extend through the interlayer insulating film. To provide this structure, the following sequence of steps must be performed for each layer of the chip.
First, a low dielectric-constant insulating film is formed on the entire surface. Next, a peripheral part of the insulating film is removed. Then, an SiO
2
insulating film is formed in the removed region. Further, a via and a pad are formed. Obviously, many steps must be performed to manufacture the semiconductor device. This inevitably decreases the productivity.
As described above, low dielectric-constant interlayer insulating films are soft and fragile and likely to be deformed or cracked when pads are connected to the external portion. If deformed or cracked, they will degrade the reliability and characteristics of the device. To prevent the reliability and characteristics of the device from being degraded, it is proposed that an ordinary insulating film, such as SiO
2
film, be formed in only the peripheral region of the chip, where pads are provided. Since pads and conductive portions are formed at each layer, however, many steps must be performed to manufacture the semiconductor device. This inevitably decreases the efficiency of manufacturing the semiconductor device.
BRIEF SUMMARY OF THE INVENTION
According to a first aspect of the invention, there is provided a semiconductor device, comprising: a substrate; a first region provided on the substrate and comprising a first insulating portion which includes an insulating film having a relative dielectric constant of at most 3.0 and a conductive portion which is provided in the first insulating portion; a second region provided on the substrate, located adjacent to the first region in a direction parallel to a major surface of the substrate and comprising a second insulating portion which is located adjacent to the first insulating portion in the direction and which includes no insulating film having a relative dielectric constant of at most 3.0; and a pad provided on the second region and electrically connected to the conductive portion.
According to a second aspect of the invention, there is provided a method of manufacturing a semiconductor device, comprising: stacking a plurality of insulating films each having a relative dielectric constant of at most 3.0 in first and second regions which are provided on a substrate and which are located adjacent to each other in a direction parallel to a major surface of the substrate; removing those parts of the plurality of insulating films, which lie in the second region, to make a hole in the plurality of insulating films; forming an insulating film having a relative dielectric constant greater than 3.0 in the hole; and forming a pad above the insulating film having a relative dielectric constant greater than 3.0.
REFERENCES:
patent: 6346471 (2002-02-01), Okushima
patent: 6465112 (2002-10-01), Ikura
patent: 2000-340569 (2000-12-01), None
patent: 2001-267323 (2001-09-01), None
Matsunaga et al.; “Wiring Structure of Semiconductor Device”; U.S. patent application No. 09/527,222, filed Mar. 16, 2000.
Finnegan Henderson Farabow Garrett & Dunner L.L.P.
Kabushiki Kaisha Toshiba
Potter Roy
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