Delay locked loop circuit interoperable with different...

Details Delay locked loop circuit interoperable with different... Delay locked loop circuit interoperable with different...

2003-08-05

2004-12-07

Nguyen, Minh (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synchronizing

C331SDIG002, C375S376000

Reexamination Certificate

active

06828835

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to a Delay Locked Loop (DLL) circuit; and, more particularly, to a DLL circuit used in an Application Specific Integrated Circuit (ASIC) or a Double Data Rate Synchronous Dynamic Random Access Memory (DDR SDRAM) for eliminating clock skew.
DESCRIPTION OF RELATED ART
Generally, a DLL circuit is used for synchronizing an internal clock distributed in a semiconductor memory device and an external clock from chipset. That is, when the external clock is used in the chip, timing skew occurs. The DLL circuit synchronizes the internal clock and the external clock by controlling the time-delay step in the variable delay line.
FIG. 1
is a block diagram showing a conventional delay locked loop (DLL) circuit.
The conventional DLL circuit includes a delay modeling unit
110
, a phase detector
120
, a counter and a decoder
130
and a digital delay line
140
.
The delay modeling unit
110
is a replica path (tAC path) from input clock to output. The phase detector
120
compares the phase of the feedback clock with the external clock, and generates a shift-indicate signal. The counter and the decoder
130
generate a shift-control signal in order to control an amount of delay according to the former signal. The digital delay line
140
has a variable delay according to the shift-control signal, and outputs the skew-compensated clock to the delay modeling unit
110
.
In the case of manufacturing the DDR SDRAM which is used for both a main memory and a graphic memory with the conventional DLL circuit, the DDR SDRAM has to be manufactured by using different manufacturing processes or test programs according to the applications of DDR SDRAM's, since a main memory or a graphic memory has a different clock speed and requires a different logic scheme.
Generally, a fuse or an anti-fuse is equipped with the DDR SDRAM in order to decide the applications of DDR SDRAM; whether it is used for a main memory or a graphic memory. The fuse has to be cut at a wafer level, while the anti-fuse is used after a binning process at a package level. The conventional methods of manufacturing a memory device mentioned above have several disadvantages. At first, a considerable amount of yield loss occurs at the wafer level. Secondly, it takes long time to program the anti-fuse at the package level. Finally, the fuse must be completely disconnected for reducing the yield loss.
Therefore, the conventional methods are very complicate to manage the manufacturing process and a great deal of manufacturing cost is needed.
SUMMARY OF THE INVENTION
It is, therefore, a primary object of the present invention to provide a new DLL circuit which is interoperable with different applications of those products by controlling the counter of the DLL circuit according to the clock frequency of each product.
In accordance with one aspect of the present invention, there is provided a DLL circuit including: a clock buffer for receiving an external clock signal and outputting the external clock signal; a first frequency divider for receiving the external clock signal and dividing the external clock frequency according to a dividing control signal; a phase detector for receiving the divided clock signal from the first frequency divider and the external signal from the clock buffer, detecting phase delay of two signals, generating a first comparison signal and a second comparison signal and generating a sample clock signal in order to perform sampling of the second comparison signal; a DLL controller for receiving the sample clock signal and the second comparison signal from the phase detector, outputting a dividing control signal at a second logic level in a high speed operation and outputting a dividing control signal at a first logic level in a low speed operation by analyzing the sample clock signal and the second comparison signal; a delay line for receiving the external clock signal from the clock buffer and the first comparison signal and the second comparison signal from the phase detector, performing shifting of the external clock signal to the left or right according to the first comparison signal and the second comparison signal, and outputting an internal clock signal; a second frequency divider for receiving the internal clock signal from the delay line and dividing the internal clock signal according to the dividing control signal; and a replica unit for receiving the divided internal signal from the second frequency divider, compensating the time delay between the external clock and the internal clock and generating the compensation clock signal.


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