Synchronizing data streams in a graphics processor

Details Synchronizing data streams in a graphics processor Synchronizing data streams in a graphics processor

2002-02-26

2004-12-21

Bella, Matthew C. (Department: 2671)

Computer graphics processing and selective visual display system

Computer graphic processing system

Plural graphics processors

C345S520000, C345S522000, C345S556000

Reexamination Certificate

active

06833831

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates generally to the field of computer graphics and, more particularly, to render pipelines.
2. Description of the Related Art
With each new generation of graphics system, there is more image data to process and less time in which to process it. This consistent increase in data and data rates has led system architects to develop an open architecture facilitating the employment of one or more graphics accelerators. In many instances these graphics accelerators are capable of operating semi-autonomously, with only high-level direction from the host computer or microprocessor.
Graphics accelerators capable of performing semi-autonomously act as co-processors, receiving relatively few high-level instructions and parameters from the host, and in turn generating a multitude of displayable pixels or samples. One example of such an operation would be the drawing of a geometric primitive. The host may instruct the graphics accelerator to display a triangle, and may furnish the coordinates of the triangle's vertices. Optionally, the host may also provide color, lighting, transparency and texture information, defining the visual presentation of the triangle. From this small amount of information, the graphics accelerator may independently generate hundreds or thousands of pixels to draw the desired triangle.
Despite the high level of operational autonomy presented by the graphic accelerator, there may still be the need for the host to directly examine or manipulate pixels within the systems graphics buffer. In order to satisfy this need in an effective manner, an alternate data pathway may be provided between the host and the memories of the graphics accelerator. This alternate pathway may share common resources with the normal processing pathways within the graphics accelerator, creating the potential for resource contention.
The potential contention problem is further complicated in a highly pipelined graphics system. In such a system, a stream of pixels or samples may be generated (e.g., as part of geometric primitive rasterization) and placed into a processing pipe, which may represent a multiplicity of process steps or stages, each separated from the next by a clocked register. In a complex system, multiple pipes may exist in parallel, each processing portions of the same data, or performing different functions such as adding lighting effects or surface texturing.
If any portion of the processing pipelines represents common resources shared with the alternate pathway to the host, then direct accesses by the host may determine the disposition of data in process and queued in the pipelines. The disposition of this in process data should be handled carefully to mitigate data loss, and hence the display of erroneous pixels. Furthermore, the contention resolution should be quick and efficient to prevent the unnecessary stalling of the host processor. Therefore, for these reasons, a method for synchronizing data streams in a graphics processor is highly desired.
SUMMARY OF THE INVENTION
The problems set forth above may at least in part be solved in some embodiments by a method for synchronizing data streams in a graphics processor. In one embodiment, the method may include suspending a first process. The suspension of the first process may be executed in a non-destructive manner, allowing any in-process commands or data to continue along a normal course of execution to completion. In some embodiments, the in-process commands and data may be traversing a processing pipeline, wherein this pipeline may split into multiple segments, with pre-determined categories of commands and data routed to each of the various segments. In some embodiments, these multiple segments may rejoin at some downstream point in the processing pipeline. After the first process has been suspended, a special synchronization command (also referred to herein as a sync command or a sync signal) may be issued to the hardware processing block tasked with the execution of the first process. In one embodiment, this synchronization command may be a non-executable command, and may be conveyed through the hardware processing block with no alteration and placed into the processing pipelines. In the pipeline, the synchronization command may follow any pending commands and data through the various hardware processing blocks of the graphics processor. At a predetermined point downstream in the processing pipeline, the arrival of the synchronization command may be detected, and in response, a signal generated indicating that the pipeline has been “drained” of pending commands and data. In response to the indication of the pipeline being drained, a command may be issued to initiate a second process.
In some embodiments, the second process may represent the access of resources within the graphics processor by a host microprocessor or system. These resources may be shared with the first process. In these embodiments, the detection site of the synchronization command may be located on the downstream side of the shared resources, ensuring the draining of the pipeline above.


REFERENCES:
patent: 6329996 (2001-12-01), Bowen et al.
patent: 6636214 (2003-10-01), Leather et al.
patent: 2002/0085007 (2002-07-01), Nelson

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