Stacked cell design for 16-megabit DRAM array having a pair of i

Details Stacked cell design for 16-megabit DRAM array having a pair of i Stacked cell design for 16-megabit DRAM array having a pair of i

1990-01-29

1991-04-02

James, Andrew J.

357 51, 357 59, 357 71, H01L 2968, H01L 2978, H01L 2992

Patent

active

050050729

ABSTRACT:
A stacked cell design for the 16-megabit generation of DRAMs having a cell capacitor comprising a pair of interconnected doped poly storage-node plate layers which insulatedly enfold a single field plate layer and connect to the cell's storage node junction. This triple-layer stack utilizes separate polycrystalline silicon (poly) layers for the lower storage-node plate and the field plate. These two poly layers are dielectrically-insulated by a first nitride layer, and each is patterned by separate masks. Following the deposition of a second nitride layer and a third poly layer on top of the field plate layer, a channel is etched in a direction parallel to the array column, through to the first nitride layer. A portion of the lower storage-node plate layer is covered only by the first nitride layer in this channel region. The edges of the field plate layer and the edges and upper surface of the third poly layer are then oxidized, and exposed portions of the first nitride layer are then etched away, as is the oxide covering the third poly layer. A fourth poly layer is then deposited on top of the third poly layer, over the oxidized edge of the field-plate layer and on top of a portion of the now-exposed lower storage-node plate, following which the two uppermost poly layers are simultaneously conductively doped. These two uppermost poly layers are then patterned with a photoresist mask and etched to create an upper storage-node plate.

REFERENCES:
patent: 4685197 (1987-08-01), Tigelaar et al.
patent: 4864464 (1989-09-01), Gonzalez

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