Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Ball or nail head type contact – lead – or bond
Reexamination Certificate
2002-05-01
2004-02-17
Donovan, Lincoln (Department: 2832)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Ball or nail head type contact, lead, or bond
C257S672000, C257S783000, C257S737000
Reexamination Certificate
active
06693363
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to board-on-chip and chip-on-board ball grid array, including fine ball grid array, semiconductor chip packages. The present invention more particularly relates to constructing ball grid array semiconductor chip packages that are particularly suitable for being burned-in and tested in a more efficient and cost-effective manner. The subject invention further provides stackable ball grid array semiconductor chip packages which may be used to form highly dense, low-profile microelectronic components in which the semiconductor chip, or device, is better protected.
2. State of the Art
Ball grid array (BGA), including fine ball grid array (FBGA), semiconductor device packages are well known in the art. For convenience, a representative prior art BGA package is shown in drawing
FIGS. 1 through 3
. BGA chip packages, such as exemplary chip package
10
, often comprise a substrate
12
, such as a printed circuit board, having an elongated aperture
14
extending through the middle thereof. A semiconductor die
16
, such as a dynamic random access memory (DRAM) device for example, is mounted on the opposite or bottom side of the substrate which is not viewable in drawing FIG.
1
. Semiconductor die or device
16
most often will have a plurality of bond pads
20
in single column or multiple columns on an active surface
18
of semiconductor die
16
. The active surface
18
of semiconductor die
16
is shown facing upward and can be viewed through aperture
14
in drawing FIG.
1
. Substrate
12
is provided with an upwardly facing top surface
22
, as shown in drawing
FIG. 1
, having a plurality of contact or bond pads
24
located along the periphery of aperture
14
. Circuit traces
26
located on or within substrate
12
serve to electrically connect bond pads
20
to respective electrically conductive, connective elements such as solder balls
28
. The electrically conductive elements typically comprise solder balls in electrical communication with and attached to a contact pad (not shown in FIGS.
1
-
3
), or can merely be a solder ball placed directly upon, or in electrical communication with, the termination point of a selected circuit trace
26
. Gold filled or other conductive metal-based solder balls are frequently used. Alternatively, conductive balls made of a conductive-filled epoxy material having specifically preselected conductive qualities are also frequently used. The conductive elements or balls are arranged in a grid array pattern wherein the conductive elements or solder balls
28
are of a preselected size or sizes and are spaced from each other at one or more preselected distances, or pitches. Hence, the term “fine ball grid array” (FBGA) merely refers to a particular ball grid array pattern having what are considered to be relatively small conductive elements or solder balls
28
being spaced at very small distances from each other resulting in dimensionally small spacings or pitch. As generally used herein, the term “ball grid array” (BGA) encompasses fine ball grid arrays (FBGA) as well as ball grid arrays. Typical solder ball sizes can be approximately 0.6 mm or less and the solder balls may have a spacing or pitch of approximately 0.80 mm or less. However, the present invention is not limited with respect to a particular solder ball diameter or pitch.
Contact or bond pads
20
on active surface of semiconductor die
16
are electrically and, to an extent mechanically, attached to respective contact pads
24
located on reactive surface of substrate
12
by way of respective bond wires
30
by wire bonding methods known and practiced within the art.
Referring now to drawing
FIGS. 2 and 3
, which are cross-sectional views taken along line
2
/
3
—
2
/
3
as shown in drawing
FIG. 1
, bottom side or surface
32
of substrate
12
and nonactive side
36
of die
16
are denoted. Semiconductor die or device
16
is attached to bottom side
32
of substrate
12
by any suitable adhesive
34
. Illustrated in drawing
FIG. 3
is an encapsulant
38
disposed over contact pads
24
, bond wires
30
, and bond pads
20
so as to protect and secure the somewhat fragile bond wires and bond sites from environmentally induced corrosion or other physical harm during immediately subsequent processing, storage, shipment, further processing, and ultimately during end use.
For quality control purposes, as well as manufacturing efficiency, it is standard practice to burn-in and electrically test semiconductor chip packages, such as representative prior art chip package
10
, prior to installing the packages on the next-higher level of assembly, such as upon a dual in-line memory module (DIMM). Those chip packages that do not successfully undergo burn-in and testing are either reworked and retested or scrapped in accordance with economic feasibilities of the particular chip package being manufactured. In order to perform such pre-installation burn-in and testing, that is, intentionally subjecting the packages to elevated voltages and temperatures and then running preliminary, and perhaps diagnostic, tests on BGA chip packages such as BGA chip package
10
, the chip packages must be mounted in specifically designed test tooling. A simplified illustration of representative test tooling
40
is shown in drawing FIG.
4
. Generally, each BGA chip package
10
is placed in chip-receiving cell
44
of tray or holder
42
. Chip package
10
usually has, but may not have, encapsulant
38
disposed thereon at the time of burn-in and testing. Upon chip package
10
being properly seated in tray
42
, probe head
46
is moved toward chip package
10
in the direction of the arrow so as to engage each probe
48
with a corresponding conductive element such as solder ball
28
. Upon BGA chip package
10
being burned-in and tested, probe head
46
is withdrawn from the chip package and the chip package is removed from test tray or holder
42
and forwarded on for further processing depending on the test results.
Because there are typically a large number of such solder balls to be contacted by a like number of probes for each chip package which must be arranged in a precise array or pattern in order to make electrical contact with the underlying solder balls, the test tooling is quite expensive, as well as time consuming, to construct. The time and expense factors of providing specific test tooling for each type of BGA chip having a wide variety of ball grid array patterns is compounded when the particular BGA chips to be burned-in and tested are of the fine ball grid array variety wherein the balls and spacing are quite small, thereby making the construction of the chip package test tooling even more time consuming and expensive. Furthermore, the specific test tooling to be devised must not only accommodate, burn-in, and test a single chip package, but must also be able to simultaneously accommodate, burn-in, and test a significant number of other chip packages, which may or may not have been segmented from a common substrate and are usually positioned and accompanied by respective cells of test tooling so that production quantities can be produced economically. Thus, it can be appreciated that the time and expense of constructing BGA chip package test tooling, which by necessity has a multiplicity of probes specifically sized and arranged in patterns which must exactly correspond to the respective solder ball array being tested, are significant hindrances to quickly introducing BGA chip packages and, in particular, FBGA chip packages having new and different solder ball array patterns to the very competitive semiconductor chip marketplace. Furthermore, the test probes of the test tooling must be designed not to unduly damage the solder balls which will ultimately be used to electrically and mechanically connect the chip package to the next level of assembly by solder ball attachment methods used within the art.
U.S. Pat. No. 5,977,784, issued to Pai on Nov. 2, 1999, and related U.S. Pat. No. 5,
Fook Jeffrey Toh Tuck
Tay Wuu Yean
Donovan Lincoln
Lee K.
Micro)n Technology, Inc.
TraskBritt
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