Semiconductor memory device

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357 42, 357 51, H01L 29040, H01L 27020

Patent

active

050050680

ABSTRACT:
A static RAM having first word lines each defined by extended gate electrodes of MISFETs constituting memory cells, and second word lines which are separate from the first word lines. The RAM has a wiring for supplying a fixed potential such as a ground potential to the memory cells, the wiring being formed from the same layer as that for forming the second word lines.

REFERENCES:
patent: 4209716 (1980-06-01), Raymond, Jr.
patent: 4291328 (1981-09-01), Lien et al.
patent: 4453175 (1984-06-01), Ariizumi et al.
patent: 4488166 (1984-12-01), Lehrer
patent: 4604641 (1986-08-01), Konishi
patent: 4710892 (1987-12-01), Masuoka et al.
patent: 4774203 (1988-09-01), Ikeda et al.
Ochii, et al., "A 17ns 64K CMOS RAM with a Schmitt Trigger Sense Amplifier", ISSCC Digest of Technical Papers, pp. 64-65; Feb. 13, 1985.

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