Static information storage and retrieval – Floating gate – Particular biasing
Reexamination Certificate
2001-12-12
2004-12-21
Nelms, David (Department: 2818)
Static information storage and retrieval
Floating gate
Particular biasing
C365S185180, C365S072000, C711S103000
Reexamination Certificate
active
06834013
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of Invention
The present invention relates to a method for programming and erasing a non-volatile memory. More particularly, the present invention relates to a method for programming and erasing a non-volatile memory with a nitride tunneling layer.
2. Description of Related Art
The family of the non-volatile memory includes the erasable programmable read-only memory (EPROM) and the electrically erasable programmable read-only memory (E
2
PROM). Particularly, the E
2
PROM can be erased and programmed electrically and is capable of retaining data even if the power is turned off, and therefore is widely used in personal computers and in electronic apparatuses.
The E
2
PROM with a silicon oxide/silicon nitride/silicon oxide (ONO) stacked structure is recently developed, which includes the Silicon-Oxide-Nitride-Oxide-Silicon (SONOS) memory and the nitride read-only memory (NROM). By comparing with the conventional non-volatile memory having a doped polysilicon floating gate, the SONOS memory uses lower voltages for its operation and therefore can be easily scaled down for a higher integration. On the other hand, the NROM is able to prevent a leakage and to store two bits in one memory cell, and therefore has a better performance. A typical NROM is capable of preventing a leakage is because the injected electrons are localized in certain regions in the silicon nitride charge trapping layer. These injected electrons are less likely to locate on the defects in the tunnel oxide layer that would otherwise cause a leakage.
However, since the SONOS memory and the NROM both use silicon oxide as the material of the tunneling layer, the following problems are encountered.
Since silicon oxide has a high energy barrier for an electron and an electron hole, the efficiency of hot carrier (electron or electron hole) injection through the tunnel oxide layer is low when the channel hot carrier injection mechanism is used to program or to erase the SONOS or NROM device. Thus the rates of the programming operation and the erasing operation of the memory device are lowered.
SUMMARY OF THE INVENTION
Accordingly, this invention provides a method for programming and erasing a non-volatile memory with a nitride tunneling layer, which can promote the efficiency of a programming operation or an erasing operation of a memory device.
The method for programming a non-volatile memory with a nitride tunneling layer of this invention comprises the following steps. The gate of the non-volatile memory is applied with a first voltage and the substrate is grounded to turn on the channel between the source and the drain. The drain is applied with a second voltage and the source is grounded to induce a current in a channel and thereby generate hot electrons therein. The hot electrons are injected into a charge-trapping layer of the non-volatile memory and trapped therein through the nitride tunneling layer.
The method for erasing a non-volatile memory with a nitride tunneling layer of this invention comprises the following steps. The drain is applied with a first positive bias, the gate is applied with a second positive bias, and the substrate and the source are both grounded to generate hot electron holes in the channel region. The hot electron holes are injected into the charge-trapping layer through the nitride tunneling layer and are recombined with the electrons therein to complete the erasing operation.
Moreover, in the method for programming and erasing a non-volatile memory with a nitride tunneling layer of this invention, the first voltage, the second voltage, the first positive bias, and the second positive bias mentioned above are all lower than those used in the operation of the SONOS memory of the same size.
Since the tunneling layer in this invention is made from silicon nitride that has a energy barrier lower than that of silicon oxide used in the prior art, the efficiency of the channel hot carrier injection can be promoted and the operating rates of the memory device are thus increased.
Besides, since the dielectric constant of silicon nitride is higher than that of silicon oxide, lower operating voltages can be used to program or to erase the nonvolatile memory with a nitride tunneling layer. Therefore, the critical dimension and the size of a memory cell can be further reduced for a higher integration.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.
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Chan Kwang-Yang
Fan Tso-Hung
Liu Mu-Yi
Lu Tao-Cheng
Yeh Yen-Hung
J.C. Patents
Macronix International Co. Ltd.
Nelms David
Pham Ly Duy
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