Static information storage and retrieval – Addressing – Sync/clocking
Reexamination Certificate
2003-09-25
2004-06-22
Phan, Trong (Department: 2818)
Static information storage and retrieval
Addressing
Sync/clocking
C365S230030
Reexamination Certificate
active
06754134
ABSTRACT:
BACKGROUND OF INVENTION
1. Field of the Invention
The present invention relates to a semiconductor storage device and, more particularly, to a semiconductor storage device having a multiple burst interrupt feature for switching burst operations on a priority basis.
2. Background of the Invention
FIG. 11
shows the layout of the entire configuration of a conventional DDR (Double Data Rate) type SDRAM (Synchronous Dynamic Random Access Memory). Referring to
FIG. 11
, the SDRAM shown includes four banks, BNK
0
through BNK
3
, utilizes a 16-bit data bus for input and output of data and has a memory capacity of 256 Mbits.
Each bank BNKi (i=0 to 3) has 8K word lines (not shown), 8K pairs of bit lines (not shown) and 8K sense amplifiers (not shown), and has a memory capacity of 64 Mbits. Each bank BNKi inputs and outputs 16-bit data.
Each bank BNKi is divided into 16 arrays.
FIG. 11
representatively illustrates arrays ARY
2
and ARY
3
of the bank BNK
0
and an array ARY
1
of the bank BNK
1
. Each array has 512 word lines, 8K pairs of bit lines and 8K sense amplifiers, and has a memory capacity of 4 Mbits. Each array inputs and outputs 16-bit data.
The SDRAM has a burst interrupt feature for interrupting a burst operation to start another burst operation. The burst interrupt feature will be explained, referring to the timing chart shown in
FIG. 12. A
burst read operation is shown with a CAS (Column Address Strobe) latency set to 2 clock cycles and a burst length of 8 bts. Since this SDRAM is the DDR type, it is capable of substituting 8-bit burst data by another 8-bit burst data storing at an odd position of the burst data. Specifically, burst data after the 3rd bit, 5th bit or 7th bit can be replaced by another burst data.
First, a command RAS
1
is issued. The command RAS
1
means inputting a row address in response to a RAS (Row Address Strobe). In response to the row address input by the command RAS
1
, a bank BNK
1
is activated, and an array ARY
1
in the bank BNK
1
is activated. In this case, by the time the array ARY
1
in the bank BNK
1
is activated, the bank BNK
0
has already been activated and an array ARY
2
in the bank BNK
0
has been activated.
Subsequently, a command R
1
CAS
1
is issued. The command R
1
CAS
1
means inputting a column address in response to a CAS. A burst read operation starts following two clocks from the command R
1
CAS
1
. Specifically, in an array ARY
1
in the activated bank BNK
1
, data is consecutively read, beginning with the column address input by the command R
1
CAS
1
.
Subsequently, when a command R
2
CAS
1
is issued following two clock cycles from the command R
1
CAS
1
, another burst read operation begins following two clock cycles from the command R
2
CAS
1
. Specifically, in an array ARY
2
in another bank BNK
0
, data is consecutively read, beginning with the column address input by the command R
2
CAS
1
.
At this time, the burst read operation started in response to the command R
1
CAS
1
is interrupted by the burst read operation started in response to the command R
2
CAS
1
. Specifically, the burst read operation begun in response to the command R
1
CAS
1
is interrupted after the data of a 4th bit is read, and the data of a 5th bit and after is replaced by the data read by the burst read operation begun in response to the command R
2
CAS
1
.
Next, when a command R
2
CAS
2
is issued, following two clock cycles from the command R
2
CAS
1
, another burst read operation begins following two clock cycles from the command R
2
CAS
2
. Specifically, in array ARY
2
in the same bank BNK
0
, data is consecutively read, beginning with another column address input by the command R
2
CAS
2
.
At this time, the burst read operation started in response to the command R
2
CAS
1
is interrupted by the burst read operation started in response to the command R
2
CAS
2
. Specifically, the burst read operation begun in response to the command R
2
CAS
1
is interrupted after the data of the 4th bit is read, and the data of the 5th bit and after is replaced by the 8-bit data read by the burst read operation begun in response to the command R
2
CAS
2
.
Thus, even when a burst read operation is interrupted, the conventional SDRAM is capable of seamlessly outputting data if a new address input by the interruption is either a column address in another bank already activated or another column address currently being activated in the same array in the same bank. If, however, the new address is a column address other than the above, then seamless output of data cannot be realized.
For example, if an address is changed from array ARY
2
to another array ARY
3
even in the same bank BNK
0
, the array ARY
2
must be first pre-charged to be activated in response to the command PRC
1
, then array ARY
3
must be activated in response to a command RAS
3
. In this case, an 8-bit burst read operation begins only after two clocks following a command R
3
CAS
3
. This causes a gap equivalent to 8 bts to be produced in burst data to be output, resulting in a lower data rate.
The burst read operation interrupt occurs when priority is assigned to a computer program other than the currently executing computer program. In this case, a new address input for the interrupt is seldom a column address in the same row address. Therefore, the burst interrupt feature provided in the conventional SDRAM can rarely be utilized effectively.
In the case of the SDRAM shown in
FIG. 11
, if one of the sixteen arrays is selected and one word line in the selected array is activated, then 8K sense amplifiers are activated. Since the SDRAM has sixteen inputs/outputs, the page length per input/output is 512 (=8K÷16) bits. In other words, there are only 512 addresses allowing seamless interrupt to be handled. Even if all four banks BNK
0
to BNK
3
are activated, there are only 2K (=512×4) addresses permitting seamless interrupt to be accomplished. This number is extremely limited for the total number of addresses 16M (=256M÷16) per input/output. The probability of successful seamless interrupts depends on the address space ratio (2K/16M), and is only 0.012%. This means that 99.998% of burst operation interrupt requests cannot be seamlessly handled. In most cases, therefore, a gap occurs in burst data to be output, resulting in a lower data rate.
Japanese Unexamined Patent Application Publication No. 2000-195253 (U.S. Pat. No. 6,252,794) has disclosed an SDRAM adapted to shorten a gap between burst operations by activating only the quantity of sense amplifiers corresponding to a burst length. The application, however, does not at all refer to a burst operation interrupt.
In the above description, the problems with the burst interrupt feature have been explained, taking the burst read operation as an example. The same problems are observed, however, also with a burst write operation.
SUMMARY OF INVENTION
An object of the present invention is to provide a semiconductor storage device permitting seamless input/output of data even when an interrupt takes place during a burst operation.
Another object of the present invention is to provide a semiconductor storage device having a higher probability of a valid interrupt for switching, on a priority basis, to a second burst operation while processing a first burst operation.
A semiconductor storage device according to one aspect of the present invention has a plurality of arrays, a plurality of burst read circuits, and a burst interrupt circuit. The plurality of arrays are activated independently from each other. The plurality of burst read circuits are provided, corresponding to the plurality of arrays. Each of the burst read circuits successively reads a plurality of bits of data from its corresponding array. The burst interrupt circuit activates a first burst read circuit while a second burst read circuit is activated.
In the semiconductor storage device, the arrays are activated independently from one another. Hence, an interrupt can be accepted while a plurality of bits of data is being succ
Canale Anthony J.
International Business Machines - Corporation
Phan Trong
LandOfFree
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