Active solid-state devices (e.g. – transistors – solid-state diode – Gate arrays – With particular signal path connections
Reexamination Certificate
2001-11-20
2004-08-31
Tran, Minh-Loan (Department: 2826)
Active solid-state devices (e.g., transistors, solid-state diode
Gate arrays
With particular signal path connections
C257S209000, C257S210000, C257S295000, C257S296000
Reexamination Certificate
active
06784468
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a ferroelectric memory in which a plurality of memory cells each having a transistor and a ferroelectric capacitor are arranged in a matrix.
FIG. 25
shows a circuit configuration of a ferroelectric memory common to first and second conventional examples and embodiments of the present invention. As shown in
FIG. 25
, a ferroelectric memory cell is of a one-transistor one-capacitor type having one transistor and one ferroelectric capacitor. A gate electrode of the transistor of the ferroelectric memory cell is connected to a word line and a drain electrode of the transistor is connected to a bit line. One electrode of the capacitor of the ferroelectric memory cell is connected to a plate line and the other electrode of the capacitor is connected to a source electrode of the transistor. Thus, the ferroelectric memory cell is controlled by signals applied to the plate line, the word line and the bit line.
(First conventional example)
Hereinafter, a ferroelectric memory of the first conventional example will be described with reference to
FIGS. 26
,
27
and
28
.
FIGS. 26 and 27
show a layout of a ferroelectric memory cell array in the first conventional example, and
FIG. 28
shows a cross-sectional structure taken along line D—D of
FIGS. 26 and 27
. Note that
FIG. 27
is a view showing only active regions, word lines, bit line contacts and storage node contacts taken from the layout of FIG.
26
.
Referring to
FIGS. 26
,
27
and
28
, the reference numerals
11
a
,
11
b
,
11
c
and
11
d
denote plate lines constructed of upper electrodes of ferroelectric capacitors. The reference numerals
12
a
,
12
b
,
12
c
and
12
d
denote word lines made of polycrystalline silicon constructed of gate electrodes of access transistors. The reference numerals
13
a
,
13
b
,
13
c
and
13
d
denote bit lines made of aluminum interconnections. The reference numerals
14
a
,
14
b
,
14
c
and
14
d
denote storage nodes of ferroelectric memory cells, each constructed of a lower electrode of the ferroelectric capacitor. The reference numeral
18
denotes a one-bit ferroelectric memory cell of the one-transistor one-capacitor type, and the reference numeral
19
denotes a transistor constituting the ferroelectric memory cell
18
. The reference numeral
15
denotes storage node contacts connecting the storage nodes
14
a
,
14
b
,
14
c
and
14
d
and active regions
16
of the transistors
19
, and the reference numeral
17
denotes bit line contacts connecting the bit lines
13
a
,
13
b
,
13
c
and
13
d
and the active regions
16
of the transistors
19
.
Referring to
FIG. 26
, the reference code a
1
denotes the first inter-plate distance between the adjacent plate lines
11
a
and
11
b
with the bit line contacts
17
therebetween, b
1
denotes the line width of the plate lines
11
a
and
11
b
including the storage nodes
14
a
, and c
1
denotes the second inter-plate distance between the adjacent plate lines
11
b
and
11
c
without the bit line contacts
17
therebetween.
As shown in
FIG. 26
, the storage node contact
15
and the bit line contact
17
are placed at the shortest distance from each other via the active region
16
.
(Second conventional example)
Hereinafter, a ferroelectric memory of the second conventional example will be described with reference to
FIGS. 29
,
30
and
31
.
FIGS. 29 and 30
show a layout of a ferroelectric memory cell array in the second conventional example, and
FIG. 31
shows a cross-sectional structure taken along line E—E of
FIGS. 29 and 30
. Note that
FIG. 30
is a view showing only active regions, word lines, bit line contacts and storage node contacts taken from the layout of FIG.
29
.
Referring to
FIGS. 29
,
30
and
31
, the reference numerals
21
a
,
21
b
,
21
c
and
21
d
denote plate lines constructed of upper electrodes of ferroelectric capacitors. The reference numerals
22
a
,
22
b
,
22
c
and
22
d
denote word lines made of polycrystalline silicon constructed of gate electrodes of access transistors. The reference numerals
23
a
,
23
b
,
23
c
and
23
d
denote bit lines made of aluminum interconnections. The reference numerals
24
a
,
24
b
,
24
c
and
24
d
denote storage nodes of ferroelectric memory cells, each constructed of a lower electrode of the ferroelectric capacitor. The reference numeral
28
denotes a one-bit ferroelectric memory cell composed of one transistor and one capacitor, and the reference numeral
29
denotes the transistor constituting the ferroelectric memory cell
28
. The reference numeral
25
denotes storage node contacts connecting the storage nodes
24
a
,
24
b
,
24
c
and
24
d
and active regions
26
of the transistors
29
, and the reference numeral
27
denotes bit line contacts connecting the bit lines
23
a
,
23
b
,
23
c
and
23
d
and the active regions
26
of the transistors
29
.
Referring to
FIG. 29
, the reference code a
2
denotes the first inter-plate distance between the adjacent plate lines
21
a
and
21
b
with the bit line contacts
27
therebetween, b
1
denotes the line width of the plate lines
21
a
and
21
b
including the storage nodes
24
a
, and c
1
denotes the second inter-plate distance between the adjacent plate lines
21
b
and
21
c
without the bit line contacts
17
therebetween. The reference code d denotes the distance between one side edge of the word line
22
a
and the center of the bit line contact
27
, e denotes the line width of the word line
22
a
, and f denotes the distance between the other side edge of the word line
22
a
and the center of the storage node contact
25
. The first inter-plate distance a
2
in the second conventional example is not the shortest distance obtainable by machining the plate lines
21
a
and
21
b.
The distance between the storage node contact
25
and the bit line contact
27
is set to be the shortest via the active region
26
, which is the sum of the line width e of the word line
22
a
, the distance d between one side edge of the word line
22
a
and the center of the bit line contact
27
, and the distance f between the other side edge of the word line
22
a
and the center of the storage node contact
25
.
(Problems of the first conventional example)
In the first conventional example, the length L
11
of the ferroelectric memory cell
18
in the bit line direction satisfies L
11
=a
1
/2+b
1
+c
1
/2.
Therefore, the area S
11
of the ferroelectric memory cell
18
is represented by
S
11
=
L
11
×
W
11
=(
a
1
/2
+b
1
+
c
1
/2)×
W
11
wherein W
11
is the length of the ferroelectric memory cell
18
in the word line direction.
In general, a predetermined space is required between the edge of the plate line
11
a
,
11
b
,
11
c
or
11
d
on the side of the bit line contacts and the bit line contacts for prevention of short-circuiting therebetween. For this reason, the first inter-plate distance a
1
between the adjacent plate lines
11
a
and
11
b
with the bit line contacts
17
therebetween is greater than the second inter-plate distance c
1
between the adjacent plate lines
11
b
and
11
c
without the bit line contacts
17
therebetween, that is, a
1
>c
1
.
Therefore, in the first conventional example, the area S
11
of the ferroelectric memory cell
18
disadvantageously increases compared with the case in which all the inter-plate distances are equal to the second inter-plate distance c
1
, that is, a
1
=c
1
.
In addition, in the first conventional example, in order to drive the plate line
11
a
for read/write of data from/in the ferroelectric memory cell
18
, all of the bit lines
13
a
,
13
b
,
13
c
and
13
d
connected to the plate line
11
a
via the word line
12
a
are used simultaneously. In this occasion, since the bit lines
13
a
,
13
b
,
13
c
and
13
d
are adjacent to each other, noise is generated due to the capacitance existing between the bit lines, and this may easily cause a malfunction.
(Problems of the second conventional example)
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