Electrical computers: arithmetic processing and calculating – Electrical digital calculating computer – Particular function performed
Reexamination Certificate
2001-01-29
2004-11-09
Malzahn, D. H. (Department: 2124)
Electrical computers: arithmetic processing and calculating
Electrical digital calculating computer
Particular function performed
Reexamination Certificate
active
06816876
ABSTRACT:
BRIEF DESCRIPTION OF THE INVENTION
This invention relates to the generation of pseudo-random noise sequences. More particularly, this invention relates to modifying a pseudo-random noise sequence by either increasing or decreasing the length of the sequence. The invention is particularly useful in spread-spectrum wireless telecommunication systems and will be described in that context.
BACKGROUND OF THE INVENTION
Mobile stations of cellular and personal wireless communications systems need to acquire certain cell-specific information before negotiating service with a serving base station. The base stations are strategically placed in a geographical area (based on capacity and coverage requirements), and each base station transmits the necessary cell-specific information. In spread-spectrum systems, the cell-specific information is carried by the pilot and/or synchronization channels. The latter are spread with pseudo-random or Gold code sequences, which form the basis for mobile station frame, slot and bit timing synchronization. The sequences also identify the base station. At power-up, the mobile station needs to search over the set of known system-specific codes to identify the serving base station and to achieve frequency, time and frame/slot synchronization.
This necessitates that the mobile station be capable of storing or generating any such code. One approach involves the generation and manipulation of pseudo-random noise (PN) sequences. In particular, PN sequences are generated by an LFSR (Linear Feedback Shift Register) that includes N stages with some intervening exclusive-OR gates. The maximum length of a PN sequence generated by an LFSR with N-stages is 2
N
−1 bits. Depending on the structure of the LFSR, the generated PN sequence can also be (2
N
−1)/H bits long, where H is a factor of(2
N
−1). A maximal length PN sequence is also called an M-sequence.
A sequence length of 2
N
−1 is inconvenient because these numbers contain few factors and are frequently prime numbers. This makes it difficult to synchronize sequence generation with processes operating at a lower rate than the PN chip rate. Therefore, many spread-spectrum systems modify a generated code sequence such that its length changes from 2
N
−1 to 2
N
. Many spread-spectrum systems also include the code generation requirements of lengthening or shortening a PN sequence.
Prior art methods of lengthening or shortening PN sequences require undesirably complex control algorithms and hardware. Accordingly, there exists a need for a method and apparatus for lengthening or shortening PN sequences that does not require complex control algorithms and hardware.
SUMMARY OF THE INVENTION
An embodiment of the present invention is an apparatus for modifying a pseudo-random noise (PN) sequence with an arbitrary phase shift. The apparatus includes an N-stage linear feedback shift register (LFSR) that generates a first PN sequence. The LFSR is coupled to a first mask circuit and a second mask circuit for generating two additional PN sequences. The apparatus further includes logic for switching between the two additional PN sequences to form an output PN sequence having a phase shift relative to the first PN sequence output by the LFSR.
The method of one embodiment of the invention includes the steps of: generating a first PN sequence, generating two additional PN sequences, monitoring a state vector of the LFSR, outputting bits from a first additional PN sequence, outputting bits from a second additional PN sequence when the LFSR state vector matches a first pre-determined compare vector, and resuming output from the first additional PN sequence when the LFSR state vector matches a second pre-determined compare vector. The resulting output forms an output PN sequence having a phase shift relative to the first PN sequence.
Those skilled in the art will recognize a number of benefits associated with the disclosed technology. For example, one embodiment of the present invention provides generation of any phase-shifted PN sequence through the manipulation of two masked sequences. Functionality for both lengthening and shortening of a PN sequence is also provided. In addition, the control technique relies solely upon state comparisons to a reference state of the LFSR, without using a counter to keep track of the states of the LFSR.
Another benefit associated with the disclosed technology is that the same hardware architecture can be used to both lengthen and shorten a PN sequence.
Yet another benefit of the disclosed system is that the disclosed system may allow reconfiguration for various code requirements, and may utilize simplistic control strategies.
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Jha Uma
Medlock Joel D.
Infineon - Technologies AG
Malzahn D. H.
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